On Reducing Insertion Loss in Wavelength-Routed Optical Network-on-Chip Architecture

Lei Zhang; Yunjia Man; Xianfang Tan; Mei Yang; Ting Hu; Jianyi Yang; Yingtao Jiang

doi:10.1364/JOCN.6.000879

Journal of Optical Communications and Networking
Vol. 6,
Issue 10,
pp. 879-889
(2014)
•https://doi.org/10.1364/JOCN.6.000879

On Reducing Insertion Loss in Wavelength-Routed Optical Network-on-Chip Architecture

Lei Zhang, Yunjia Man, Xianfang Tan, Mei Yang, Ting Hu, Jianyi Yang, and Yingtao Jiang

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Lei Zhang, Yunjia Man, Xianfang Tan, Mei Yang, Ting Hu, Jianyi Yang, and Yingtao Jiang, "On Reducing Insertion Loss in Wavelength-Routed Optical Network-on-Chip Architecture," J. Opt. Commun. Netw. 6, 879-889 (2014)

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Table of Contents Category
- Research Papers
Optics & Photonics Topics
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The topics in this list come from the Optics and Photonics Topics applied to this article.
Previously assigned OCIS codes
- Networks, network topology (060.4258)
- Optical interconnects (200.4650)

About this Article
History
- Original Manuscript: April 25, 2014
- Revised Manuscript: August 18, 2014
- Manuscript Accepted: August 18, 2014
- Published: September 22, 2014

Abstract

Optical/photonic network-on-chip (ONoC) architectures are emerging as a new paradigm to interconnect a large number of processing cores at chip level, meeting the pressing demand for extremely high bandwidth and low power consumption. The micro-ring resonator is the key switching component to build such an architecture. However, there is a major concern in accumulated signal insertion loss, especially for large-scale ONoC architectures. In this paper, we propose a new method to transform the ONoC topologies such that the insertion loss can be reduced. Analytical results have confirmed the effectiveness of the proposed method in insertion-loss reduction.

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	$O_{0}$	$O_{1}$	$O_{2}$	$O_{3}$	$O_{4}$	$O_{5}$
$I_{0}$	—	$λ_{1}$	$λ_{2}$	$λ_{3}$	$λ_{4}$	$λ_{5}$
$I_{1}$	$λ_{3}$	—	$λ_{1}$	$λ_{2}$	$λ_{5}$	$λ_{4}$
$I_{2}$	$λ_{1}$	$λ_{4}$	—	$λ_{5}$	$λ_{2}$	$λ_{3}$
$I_{3}$	$λ_{4}$	$λ_{3}$	$λ_{5}$	—	$λ_{1}$	$λ_{2}$
$I_{4}$	$λ_{2}$	$λ_{5}$	$λ_{3}$	$λ_{4}$	—	$λ_{1}$
$I_{5}$	$λ_{5}$	$λ_{2}$	$λ_{4}$	$λ_{1}$	$λ_{3}$	—

	$α$
Insertion Loss (dB)	0.90	0.91	0.92	0.93	0.94	0.95	0.96	0.97	0.98	0.99	1.00
Cross near drop	3.31	3.03	2.73	2.43	2.11	1.79	1.46	1.11	0.75	0.38	0.00
Cross far drop	3.97	3.63	3.29	2.94	2.58	2.21	1.83	1.44	1.04	0.63	0.20
Cross drop average	3.64	3.33	3.01	2.68	2.35	2.00	1.64	1.28	0.90	0.51	0.10
Parallel drop	3.31	3.03	2.73	2.43	2.11	1.79	1.46	1.11	0.75	0.38	0.00
Cross through	0.20	0.19	0.19	0.18	0.18	0.17	0.17	0.16	0.16	0.15	0.15
Parallel through	0.10	0.09	0.09	0.08	0.08	0.07	0.07	0.06	0.06	0.05	0.05

	$α$
Insertion Loss (dB)	0.90	0.91	0.92	0.93	0.94	0.95	0.96	0.97	0.98	0.99	1.00
$l_{C T}$	0.20	0.19	0.19	0.18	0.18	0.17	0.17	0.16	0.16	0.15	0.15
$l_{C D}$	3.64	3.33	3.01	2.68	2.35	2.00	1.64	1.28	0.90	0.51	0.10
$l_{WPD}$	3.41	3.13	2.83	2.53	2.21	1.89	1.56	1.21	0.85	0.48	0.10

Block	MRR Switches in Block
(a)	1 parallel switch
(b)	3 parallel switches
(c)	4 cross switches
(d)	2 parallel switches and 1 cross switch
(e)	1 cross switch
gray	0

Block	Number of Blocks	Number of MRR Switches^a
(a)	3	$3 P$
(b)	$2 (n - 2)$	$6 (n - 2) P$
(c)	$(n - 2) (n - 3) / 2$	$2 (n - 2) (n - 3) C$
(d)	2	$4 P + 2 C$
(e)	$2 (n - 4) - 1$	$[2 (n - 4) - 1] C$
gray	$2 \times 3$	0

Network	$4 \times 4$	$6 \times 6$	$8 \times 8$	$10 \times 10$	$12 \times 12$	$14 \times 14$	16×16
GWOR	4C	12C	24C	40C	60C	84C	112C
RPN	4P	12P	$19 P + 5 C$	$25 P + 15 C$	$31 P + 29 C$	$37 P + 47 C$	$43 P + 69 C$
Network	$5 \times 5$		$7 \times 7$	$9 \times 9$	$11 \times 11$	$13 \times 13$	$15 \times 15$
GWOR	8C		18C	32C	50C	72C	98C
RPN	8P		$16 P + 2 C$	$21 P + 11 C$	$27 P + 23 C$	$33 P + 39 C$	$39 P + 59 C$

Abstract

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Equations (26)

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