Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group

A New Optical Network-on-Chip Architecture for Chip Multiprocessor

Not Accessible

Your library or personal account may give you access

Abstract

A screwy torus topology (STorus) is proposed to improve the performance of network that memory access oriented. STorus divides an optical network into two subnets, and employs waveguide hierarchy. Comparisons between STorus and mesh are made, connecting with 4 memory controllers.

© 2015 Optical Society of America

PDF Article
More Like This
A High-Performance Optical Network-on-chip Architecture Based on Sub-network Division

Ke Chen, Huaxi Gu, Zheng Chen, and Na zhang
AW3H.5 Asia Communications and Photonics Conference (ACP) 2013

A Nesting Ring Optical Network on Chip (ONoC) Architecture for Multi-chip Systems

Wenzhe Li, Shanguo Huang, Yu Zhou, Shan Yin, Jie Zhang, and Wanyi Gu
ASu1H.1 Asia Communications and Photonics Conference (ACP) 2015

Multiprocessor Architectures using Partitioned Optical Passive Star Interconnection Networks

James P. Teza, Donald M. Chiarulli, Steven P. Levitan, and Rami G. Melhem
OMB3 Optical Computing (IP) 1995

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All Rights Reserved