Abstract

Si epi-layers grown by chemical vapor deposition onto heavily doped Si substrates are commonly used for the circuitization of IC chips. The wafer provides mechanical support for the epi-Si and also serves as the ground plane. Control of electrostatic charging requires an array of low resistance paths between the front surface and the Si substrate. For thin epi-layers, <2 µm, local low resistance pathways are normally fabricated using high energy boron ion implants, ~ 1×10¹⁵/cm². For thicker layers, > 2-3 pm, this is difficult to achieve by standard methods.

© 1992 Optical Society of America