Abstract

SOA-based optical switches utilizing optical filtering techniques have been successfully demonstrated at ultrahigh bitrates up to 640Gbit/s [1, 2]. However, large power penalties have been observed due to degraded OSNR as well as patterning effects (PE) induced by slow carrier-lifetime limited decay processes. The PE, defined here as the ratio of the largest to the smallest switched peak pulse power [3], is usually estimated using pseudo-random binary sequence (PRBS) of length 2ⁿ-l, where bit pattern length n should be chosen such that the full extent of memory effects in the device is captured. The use of long PRBS lengths is often prohibited in experiments by the temporal multiplexing techniques used to generate the signal and in simulations by the excessive computation time needed. Whether the use of n=7 [1,2] corresponding to a PRBS length of 255 bits is sufficient to capture the full impact of PE of the switches is thus still an open issue. Here we (i) derive a simple condition for the minimum bit pattern length (ii) introduce an effective method for simulating patterning effects and prove its validity and (iii) use the method to analyse a specific configuration for high-speed signal processing.

© 2009 IEEE