Abstract

Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever increasing demand for more powerful computational systems. Recently, III–V integration on Si attracted significant research interest [1] due to the promise to merge mature Si CMOS processing technology with III–V semiconductors possessing superior material properties e.g. in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III–V optoelectronic devices in order to enable low-cost and power-efficient electronic-photonic integrated-circuits. In this regard, tremendous progress was achieved using various integration routes for laser sources including wafer bonding [2], buffer layers [3] or dislocation trapping [4].

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