Abstract

Silicon photonics (SiPh) and photonic integrated circuits (PIC) provide an increasingly important technology platform enabling the on-chip combination of photonics and electronics [1] while offering solutions for a wide range of applications, such as high-capacity networks and sensing [2], for example. As the SiPh waveguides cannot provide gain, different integration schemes of III-V compound semiconductors gain chips are necessary to enable on-chip light generation. Hybrid integration is a solution where a diced III-V gain chip is bonded on a PIC platform [3]. This approach provides the freedom to combine a multitude of different types of III-V chips on a PIC and is also compatible with current CMOS industry as the fabrication of the III-V chip is separated from the PIC production. However, one of the challenges of hybrid integration, is the alignment of the gain chip on the PIC. For low-loss operation, sub-micron alignment precision should be reached. This, however, is in part limited by the accuracy of the current dicing systems resulting in poor dimension control and a requirement for larger alignment tolerances.

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