Abstract

The objective of this presentation is to highlight the advances being made in electronic packaging and interconnection technologies, so that researchers in the optical interconnect community may have a better understanding of the actual problems and of the technologies against which they are competing. Chip-on-board technology—which employs bare die on a high density substrate—is being developed to address the technology requirements of VLSI devices currently in production and of tomorrow's 0.5-µm semiconductor devices, which will pose even greater challenges due to increases in device speeds, power, die size, and level of integration. Packaging technology will be critical not only for large mainframe or supercomputers, but also for workstations, peripherals, avionics, telecommunications, and consumer electronics, where cost, reliability, physical size, and/or testability may be at least as important as raw performance. In particular, we discuss: high lead count TAB for achieving >400 IO/chip at 4-mil pitch, copper polymide (Cu-Pi) substrates for chip-on-board packaging, electrical propagation of signals on Cu-Pi transmission lines, potential impact of superconducting transmission lines, air cooling techniques for 25-70-W chips, power distribution challenges, and test technology.

© 1989 Optical Society of America