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2 Kilobit Parallel Access Optical Chip for Memory, Logic or Switching

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Abstract

The high interconnectivity of free space optics offers the possibility of powerful new architectures for massively parallel processing and routing of digital information. We have fabricated chips containing the optical devices necessary for the implementation of many such experimental system architectures. The chips are arrays of 32 by 64 unit cells, where each cell is a reflective-mode Symmetric Self Electro-optic Effect Device (S-SEED). The S-SEED is effectively a cascadable three terminal device with all optical inputs and outputs. References [1] and [2] give detailed descriptions of the functionality of the S-SEED as a memory cell, a differential logic gate or a switching latch. Each array requires only two electrical contacts, one for a bias voltage and one for ground. Each unit cell needs two <=5 μm diameter (at a 20 μm spacing) clocked beams (for a total of 4096 per array) with an intensity uniformity within ~±15% at a wavelength within 1nm of the exciton peak wavelength (~850 nm). These are modulated to yield differential output beams with contrast ratios up to 5:1. Each S-SEED can accept two sets of differential input beams. A cell occuppies an area of 20 μm × 40 μm and the entire array size is ~1.3 mm × 1.3 mm. The optical switching energy per cell is between ~1 pJ and ~2.5 pJ, increasing as the bias voltage is increased (6V to 15V) for greater contrast (from 3:1 to 5:1). Sub-nanosecond switching times have been measured for individual devices. For data storage, ~200 nW of optical power per half-cell (or ~1 mW per array) can hold the state of a device indefinitely. This talk will include a discussion of the device and array structures and of the performance data. These chips can make possible optical computing and photonic switching experiments, heretofore existing only in the conceptual stage.

© 1989 Optical Society of America

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