Abstract

We will present a new fast binary multiplication scheme based on the use of a nonholographic parallel optical content addressable memory (CAM). The multiplication operation is performed by means of binary logarithmic addition that uses a sign/logarithm number system. Multiplication of two binary numbers a and b begins by converting them into a sign/logarithm number system. Multiplication is accomplished by adding appropriate logarithms. A 3-stage non-holographic CAM is required to implement a sign/logarithm number multiplier. By means of a Quine-McCluskey minimization method, the number of CAM's minterms are reduced. For a 7-bit binary multiplication the first CAM, reduced from 605 to 111 minterms, converts the binary numbers to sign/logarithm numbers. To add the two logarithms, a second CAM, reduced from 2519 to 270 minterms, performs a floating-point binary-carry look-ahead addition. Finally, a third CAM with 329 instead of 891 minterms, does the conversion from sign/logarithm numbers back to binary numbers. In general, the storage capacity needed for each CAM stage depends on the range of input numbers and the calculation accuracy.

© 1990 Optical Society of America