Abstract

A circuit has been constructed that is based on a cellular logic image processor (CLIP) architecture. It uses two Self electro-optic effect device (S-SEED) arrays as logic devices, optically connected in a loop with a 1-D nearest neighbor interconnect. The circuit is programmable in NAND and NOR and can implement image processing algorithms on a 16 × 8 dual rail image input with a spatial light modulator. Construction and assessment of this basic circuit is to allow investigation into generic issues in optical and mechanical design of parallel optical information processors. This will allow the implementation of more complex circuit design by using application specific devices and various local and non-local interconnection schemes. Analysis of the circuit performance and tolerances will permit an optical implementation using larger arrays. Addressing these issues is important before the complexity of this type of system can be increased.

© 1992 Optical Society of America