Abstract

We present WARRP: the core deadlock handling circuitry for a fully adaptive, deadlock recovery-based multiprocessor network router. This chip primarily demonstrates the integration of complex deadlock recovery circuitry and free-space optical channels on a monolithic GaAs-based chip. We report the design and implementation of the first generation, bit-serial, torus-connected chip employing 1400 transistors and 6 LED/photodetector pairs.

© 1997 Optical Society of America