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Smart Pixel Array Network Interface (SAPIENT) for 2D Parallel Data Packet Networks

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Abstract

We describe a SmArt PIxEl for NeTwork Interface (SAPIENT) chip that performs interfacing of processors to 2-D parallel optical free space networks. This network transfers 2-D parallel data packets between processors on digital optical channels. We assume these parallel data packets contain address information for the destination processor, similar to the format of an ATM packet network, except the packets are passed between processors in a parallel format, in a single clock cycle. Each SAPIENT chip is capable of checking the address bits of an incoming parallel data packet, re-transmitting (or downloading) the packet, and loading electronic data onto the optical network from its host processor. Each data packet arrives as a 2D page-wide (9 bits) packet of network data and can be easily scaled up to larger N × N packets. The SAPIENT demonstration chip contains a 3 × 3 array of smart pixels that provide optical detection and transmission. The SAPIENT also contains address detection and contention avoidance circuitry. In this paper, we describe the optoelectronic technology involved and the circuit function of the SAPIENT chip. We describe a SAPIENT chip in a multiple processor network and present simulation of the SAPIENT interface.

© 1997 Optical Society of America

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