Abstract

The goal of this paper is to investigate the impact that cost and yield have on the organization of optically interconnected computer architectures. To measure cost, we build analytic abstractions of the economics of the manufacturing process parameterized in terms of the individual fabrication step costs and yield, and the physical and logical architecture characteristics. These composite architecture-cost models are used to calculate the cost-optimum number of chips in a solder-bumped VCSEL array. For large shuffle-exchange networks with wide channels, the models predict that optical interconnects with VCSEL-solder-CMOS can be lower cost than the all electrically interconnected CMOS/MCM.

© 1997 Optical Society of America