Abstract

Free-space optical interconnections (FSOI), based on smart pixel technology (in which Silicon ICs are integrated with 2-D arrays of vertical cavity surface emitting lasers (VCSELs) and photodetectors) are projected to enable chip-to-chip interconnection fabrics that achieve bandwidth densities on the order of 1 Terabit/sec/cm² [1]. Scaleable global (i.e., every pair of chips is linked.) interconnection fabrics that achieve minimum bisection bandwidths in the multi-terabits/sec regime may be implemented using multiple optoelectronic integrated circuits linked to each other. This approach is the basis for the Free-space Accelerator for Switching FAST-Net approach the optical I/O from any single smart pixel array (SPA) chip, located at a lens’ focal plane, are linked to portions of the I/O arrays of all chips in the system. To achieve this, clusters of VCSELs and photodetectors are imaged onto corresponding clusters on other chips. Multiple point-to-point links are established between cluster pairs on different SPAs. The clusters are interleaved to achieve a global interconnection pattern across the multi-chip plane, thus effecting a high-density bidirectional data path between every pair of SPA chips on the MCM. SPA chips with integrated VCSEL/detector arrays that have emitter and receiver elements sizes of 10 and 50 µm, respectively, and with element-to-element spacing as small as 125 µm, have been evaluated in a prototype interconnection. To fully exploit the smart pixel I/O density, the global optical interconnection module must provide flat, high resolution, near distortion-free image fields, across a wide range of ray angles, with low optical loss.

© 2003 Optical Society of America