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Integrated Arrays of Low Power SOS Chip-to-Chip Interconnects for Efficient Parallel Communication in CMOS

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Abstract

In this paper we present an array silicon-on-sapphire (SOS) interconnects for high speed, low power communication between CMOS integrated circuits. We demonstrate integrated 1Gbps links with total power consumption below 25 mW per channel.

© 2003 Optical Society of America

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