Integrated Arrays of Low Power SOS Chip-to-Chip Interconnects for Efficient Parallel Communication in CMOS

A. Apsel; J. Liu; J. Liu; W. Chang; W. Chang; G. Simonis; G. Simonis; A. G. Andreou; A. G. Andreou

doi:10.1364/OC.2003.OWD6

Optics in Computing
OSA Trends in Optics and Photonics (Optica Publishing Group, 2003),
paper OWD6
•https://doi.org/10.1364/OC.2003.OWD6

Integrated Arrays of Low Power SOS Chip-to-Chip Interconnects for Efficient Parallel Communication in CMOS

A. Apsel, J. Liu, W. Chang, G. Simonis, and A. G. Andreou

Optics in Computing 2003

Washington, D.C. United States
16–20 June 2003
ISBN: 1-55752-750-4

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Optical Interconnects: Receivers (OWD)

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A. Apsel, J. Liu, W. Chang, G. Simonis, and A. G. Andreou, "Integrated Arrays of Low Power SOS Chip-to-Chip Interconnects for Efficient Parallel Communication in CMOS," in Optics in Computing, A. Sawchuk, ed., Vol. 90 of OSA Trends in Optics and Photonics (Optica Publishing Group, 2003), paper OWD6.

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Abstract

In this paper we present an array silicon-on-sapphire (SOS) interconnects for high speed, low power communication between CMOS integrated circuits. We demonstrate integrated 1Gbps links with total power consumption below 25 mW per channel.

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