Abstract
Fast-optical packet switching is becoming more and more viable, thanks to both the progress in device technology and in system/network architectures. In the mainframe of the RACE ATMOS project, a complete rack-mounted 2×2 switching- node demonstrator, called fiber loop memory switch (FLMS), has been developed1,2: the principle of operation3 relies on fast wavelength assignment (with wavelength converters) at the input; a wavelength-controlled fiber loop memory for cell buffering; and fast tuneable DFB filters4 for cell routing at the node outputs. At the node inputs, the incoming cells are converted to new wavelengths, belonging to a set (four in the demonstrator) coinciding with the gateable narrow band (≈10 GHz) optical filters in the fiber loop (loop length = one cell duration): depending on the contention situations occurring, the gateable filters are enabled or disabled, to buffer the cells (by letting them circulate) or to erase the corresponding memory position (Fig. 2). An electronic control reads the incoming cells tags, identifying the output addresses, and consequently manages to drive all optoelectronic devices, solving cell contentions and routing the cells to the desired outputs. The demonstrator (Fig. 1) operates at 622 Mbit/s, with wavelength spaced by 0.4 nm around 1540 nm.
© 1996 Optical Society of America
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