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Conferences > OFC > 2014 > Th2A > Th2A.9

A novel Chip-Multiprocessor Architecture with optically interconnected shared L1 Optical Cache Memory

P. Maniotis, S. Gitzenis, L. Tassiulas, and N. Pleros

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Abstract

We demonstrate a system-level CMP architecture where optical cache memories are shared among multiple processing cores through optical buses. System-level simulations show 25-45% execution time improvement and significant capacity requirements reduction through simpler memory hierarchy.

© 2014 Optical Society of America

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