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168 Gb/s Line Rate Real-Time PAM Receiver Enabled by Timing Recovery with 8/7 Oversampling in a Single FPGA

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Abstract

Demonstration of a real-time receiver working with 28 GBd at 32 GSa/s. The signal processing is done on a single FPGA. The resource-saving non-integer oversampling of 8/7 is enabled by a timing synchronization in the frequency domain.

© 2017 Optical Society of America

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