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A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation

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Abstract

A 50Gb/s-PAM4 Clock/Data Recovery (CDR) transceiver is designed in a 40nm-CMOS process. An on-chip Eye Opening Monitor (EOM) is introduced that enables adaptive reference level and timing sampling placement for non-uniform and distorted PAM4-inputs.

© 2018 The Author(s)

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