Abstract

Fully parallel processors can be designed by employing a technology that is inherently parallel, a suitable number system, and an efficient encoding scheme for handling the data. Binary number system is accepted as the best suited in electronic computers. The delay due to carry propagation in binary arithmetic makes the binary number representation a very weak candidate for an optical processor that is inherently parallel. The modified signed-digit (MSD) number system¹ satisfies the requirements of fully parallel addition and subtraction by limiting the carry propagation to one position to the left. The design of an optical MSD adder capable of performing addition/subtraction in three stages has already been proposed.² The above design is based on polarization-coded symbolic substitution. A reduction in the number of stages can be achieved by exploiting some of the unique characteristics of MSD. The optical implementation of the MSD adder with reduced number of stages is discussed in this paper. The MSD digits are coded as three different polarization states of light. Polarization-coded symbolic substitution is used to implement the adder.

© 1989 Optical Society of America