Abstract

A hardware compiler for translating descriptions of digital circuits from a hardware description language (HDL) into gate-level layouts is under development at Rutgers University. The layouts are customized for optical processors that make use of arrays of optical logic gates interconnected in free-space with regular interconnection patterns such as perfect shuffles, crossovers, or global interconnects. Specific processors that the hardware compiler supports include the S-SEED based all-optical processor developed at AT&T Bell Labs, the S-SEED based all-optical processor under development at the Photonics Center at RADC/Griffiss AFB, and the acousto-optic modulator based RISC processor under development at OptiComp Corporation.

© 1991 Optical Society of America