Abstract

In the last few years extensive efforts have gone into the development of spatial light modulators (SLMs) for the realization of massively parallel optical processors [1-3]. The silicon-PLZT SLM approach is a promising approach and has the potential of combining the computational power of silicon with the communication capacity of optical interconnects [4]. Optical interconnects utilize the third dimension normal to the processing plane to provide the advantages of high speed parallel and global interconnections among simple silicon electronic circuits performing local computational operations. Fig. 1 shows the schematics of Si/PLZT SLM. In order to take more advantage of the computational power of silicon we want to increase the number of transistors we can put in each unit cell. Several logic gates combined with some storage capability and photodetectors will find many useful applications in opto-electronic systems. In this paper we discuss the improved fabrication techniques to achieve better yield and higher unit cell complexity. We will also report on the results of fabricated unit cell arrays with various complexities.

© 1990 Optical Society of America