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Abstract
Photonic integrated circuits have garnered significant attention in recent years. To enhance the functional versatility of these devices, researchers have introduced the concept of reconfiguration into photonic integrated circuits. Inspired by field programmable gate arrays in the electrical domain, programmable photonic chips employing various topologies have been developed. However, users still encounter challenges when utilizing these devices, as they need to understand the internal structure and principles of the chip and individually adjust the tunable basic units within the topology network. In this paper, we employ the quadrilateral topological network based on the on-chip Mach–Zehnder interferometer as a black box to realize a highly self-reconfigurable optical signal processor. By leveraging this approach, we achieve positive real-valued matrix computation, optical routing, and low-loss optical energy splitting. Our demonstration effectively showcases the immense potential of on-chip programmable photonic waveguide meshes.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
With the development of artificial intelligence (AI) [1] and the Internet of Things [2], the demand for high accuracy and fast response speed in signal processing has led to the widespread utilization of technologies such as artificial neural network (ANN) [3,4] and Ising Machine [5]. Optical computing using photonic integrated circuits (PICs) offers numerous benefits including compact size, large bandwidth, low latency and low power consumption [6–9], making it an ideal computing platform. Numerous PIC-based devices have been developed, enabling applications such as microwave waveform generation [10], radio-frequency photonic filter [11] and photon differentiators [12]. However, these devices still have the shortcomings of limited flexibility and single functionality. Therefore, inspired by electric field programmable gate arrays (FPGAs), researchers aim to develop highly reconfigurable devices to streamline the design, fabrication, and testing processes of traditional PICs [13–19]. Through self-calibration algorithms, programmable photonic integrated circuits have been realized in forward-propagating on-chip networks [20]. Furthermore, the advent of topological photonic networks extends this idea to waveguide networks that can support both feedforward and feedbackward propagation. The smallest unit that makes up a topology is called a tunable basic unit (TBU), which should have the abilities of controlling the transmission path of light, stable performance, ease of tuning and large-scale integration. Mach–Zehnder interferometer (MZI) possesses all of these advantages and has already gained widespread usage while being compatible with complementary metal oxide semiconductor (CMOS) processes [21,22]. Therefore, MZI is an ideal structure for TBU among various basic on-chip integrated optical devices. Currently, existing MZI topological networks mainly include triangular [23], quadrilateral [24–28] and hexagonal [23,29–37] topological structures. Although these works have achieved the reconfigurability of system functions or structures to a certain extent, they often require users to understand the internal structure and principle of the chip, and manually configure the required functions based on the states of each TBU. When applied to control large-scale topological networks, this approach becomes inefficient due to the substantial number of TBUs involved and manufacturing errors that may exist between them.
In this paper, we present a quadrilateral topological waveguide mesh based on MZI that operates as a black box structure. Without prior knowledge of the specific chip structure, the system can automatically configure itself to achieve the desired functions, such as positive real-valued matrix computation, optical routing, and low-loss light energy splitting. This is accomplished through computer control, data collection, and analysis of the chip's input and output data, combined with the utilization of gradient descent algorithm and adaptive moment estimation (Adam) algorithm [18,38–41]. During the training process, each iteration updates the values of all variables, enhancing the training speed of the chip.
2. Principle and experimental setup
Figure 1 illustrates the specific structure and principle of the chip. In the quadrilateral network depicted in Fig. 1(a), each green rectangle represents a TBU composed of MZI. Each MZI consists of two multimode interferometers (MMIs) and two interference arms containing thermo-optical modulation electrodes. All electrodes are wire bonded to the printed circuit board (PCB). The formula in Fig. 1(b) describes the relationship between the input light fields (donated by m1 and m2) and output light fields (donated by n1 and n2) of MZI. Here, θ1 and θ2 denote phase changes resulting from light passing through the upper and lower interference arms of the MZI. M1 is the transmission matrix of MMI. M2 is the transmission matrix of interference arms. All the MMIs’ splitting ratio are fixed at 50:50, rendering φ = π/4. And Δ and θ are defined as Δ = (θ1 + θ2)/2 and θ = (θ1 - θ2)/2. By applying different voltages to the two electrodes of the MZI, different phase shifts will be obtained, corresponding to changes in θ. Depending on specific values of θ, the MZI will present three states as shown in Fig. 1(c): cross state, tunable coupler, and bar state.
Fig. 1. Specific structure and principle of the chip. (a) The structure diagram of the quadrilateral topological network. Each green rectangle in the network represents a TBU. The yellow rectangles represent the electrodes used for thermo-optical modulation in the MZI. PCB, Printed circuit board. (b) The composition and matrix expression of MZI. MMI, multimode interferometer. (c) The three states of MZI. Each green rectangle represents an MZI. The orange lines show the path of light as it enters the MZI from a port on the left.
Figure 2(a) shows a microscope image of the chip. The proposed topological network is built on a silicon-on-insulator (SOI) platform. The size of the on-chip structure is 3.29 × 2.83 mm2. The single-mode silicon waveguide has a height of 220 nm and a width of 500 nm, with a 2 µm thick buried oxide layer beneath it. The heating electrodes of MZIs are made of titanium nitride (TiN) with a thickness of 100 nm and a width of 2.5 µm, and the wires on the chip are deposited with gold. The entire structure contains 24 TBUs, each consisting of an independently adjustable MZI. All MMIs share uniform dimensions of 2.8 µm in width and 27.5 µm in length. The length of each interference arm is 340.56 µm. The total length and width of a TBU are about 385 µm and 73.5 µm, respectively. A total of 52 electrodes are included, of which 48 are thermo-optical modulated positive electrodes and the other 4 are ground electrodes connected to each other. Figure 2(b) is a photo of the chip after packaging. A thermoelectric cooler (TEC) is attached to the bottom of the PCB to maintain a stable chip temperature during the experiment.
Figure 3 is the diagram of the experimental setup. A four-channel laser source is used to generate light with a power of 12 dBm. The wavelengths of light are 1550 nm, 1550.01 nm, 1550.02 nm and 1550.03 nm. The intensity of light at each wavelength represents an element of the input vector. Using different wavelengths can eliminate the potential interference among vector elements’ calculation results at photodetectors (PDs), enhancing the stability of computations. Since the coupled grating is a polarization sensitive device, each path of light is polarized by a polarization controller (PC) to optimize the coupling efficiency. Computer-controlled optical switches (OSs) can be used for optical path selection. Additionally, to protect the chip and PDs, each path uses an attenuator (ATT) to control the energy of the light before entering the chip. The light intensities of the four selected output ports are detected by four PDs, corresponding to the elements of the output vector.
Fig. 3. Schematic of the experimental setup. The light blue and dark blue connection lines represent the transmission path of the input and output light, respectively. The gray connection lines represent the transmission path of the electrical signal. PC, polarization controller; OS, optical switch; ATT, attenuator; FPGA, field-programmable gate array; PD, photodetector.
The electrodes that control the status of the OSs, the electrical signals generated by PDs, and the PCB are all connected to an FPGA. The FPGA can be connected to the computer via a standard serial cable and controlled by a computer program. Therefore, users only need to set the training target, and the code on the computer automatically analyzes the data collected by the PDs. Based on this analysis, the program adjusts the voltage applied to the electrodes on the chip, enabling the automatic configuration of the topological network.
3. Experimental measurement
We first tested the basic parameters of the chip. Throughout experiment, the chip temperature was maintained at 24 °C. At a wavelength of 1550 nm, the single coupling loss of the grating is 5.25 dB. The resistance of a single TiN electrode is about 850 Ω. In an MZI, a π-shift power of 20 mW is obtained. Therefore, the initial voltage values of the electrodes during chip training are set as random numbers within the range of 4∼5 V.
3.1 Positive real-valued matrix computation
First, a fourth-order positive real-valued matrix T is generated by randomly assigning each element a value between 0 and 1. The column vectors of T are Ti (i = 1, 2, 3 and 4). The transmission matrix of the topological network is denoted as X. The input and output fourth-order matrices of the chip are M and N, respectively, with their column vectors represented as Mi (i = 1, 2, 3 and 4) and Ni (i = 1, 2, 3 and 4). Therefore, the matrix multiplication expression is shown as Eq. (1).
Input Mi to the chip in chronological order, and the output ports of the chip gets Ni in chronological order. To load T onto the chip, that is, to make X = T, we initially set M as the identity matrix. The similarity between N and T is calculated by the cost function (CF). CF is defined as Eq. (2).
Set the maximum number of iterations for chip training to 200. Each training consists of the following procedures. (I): Randomly initialize the voltages of all 48 electrodes. (II): Open only the first OS. (III): Perform voltage perturbation (ΔV) on each electrode individually: (a): Set the voltage of the selected electrode to (V + ΔV) and record the PD readings. (b): Set the voltage of the selected electrode to (V - ΔV) and record the PD readings. (c): Restore the voltage of the selected electrode to V. (d): Repeat processes (a) ∼ (c) for each electrode. (IV): Open only the second OS and repeat step (III). Open only the third OS and repeat step (III). Open only the fourth OS and repeat step (III). (V): Calculate CF+ by substituting the matrix N obtained after increasing ΔV for each electrode into Eq. (2). Similarly, calculate CF- by substituting the matrix N obtained after decreasing ΔV for each electrode into Eq. (2). Use the expression {(CF+ - CF-)/(2 × ΔV)} to calculate the gradient (G) of CF corresponding to the current voltage value of each electrode. (VI): Apply the Adam algorithm to G to obtain the optimized voltage values for each electrode in this iteration. Load these voltage values onto the chip. Calculate and record the current CF value. (VII): Repeat (II) ∼ (VI) until CF is not less than 0.999, or automatically exit the loop if the maximum number of iterations is reached. During training, every time the states of OSs change, all electrode voltages experience perturbations. Then, we calculate the CF uniformly and update the voltages of all electrodes in a single iteration. Compared to updating only one electrode voltage at a time when calculating G, our method can speed up the convergence of CF.
A typical training process is depicted in Fig. 4(a)∼(c). After 70 iterations, CF increased from 0.738 to 0.9992. The experimental results here are normalized data. All original elements of N obtained from the experiment are uniformly scaled by a coefficient to ensure that the sum of all elements is equal to the sum of all elements of T. Once T is successfully loaded onto the chip, the matrix operation T•M = N can be implemented by entering different matrices M.
Fig. 4. Experimental results of system function and stability. (a) CF changes during a typical chip training. With the increase of CF, the output matrix of the chip is closer to the value of the target result. The error between the final training results and the target matrix is also displayed. The initial and final voltages of the electrodes on the chip during the training process of (a) are shown in (b) and (c), respectively. (d) The statistical result of the loss of the topological network. (e) Chip stability test when temperature changes.
To demonstrate the effectiveness of our proposed system for arbitrary positive real-valued matrices, we conduct the above training process with 110 randomly generated positive real-valued matrices, all of which can be successfully loaded onto the chip in less than 200 iterations. These 110 matrices contain 440 column vectors, and we calculate the loss of these column vectors after passing through the topological network. The numerical distribution of the loss after excluding the grating loss is shown in Fig. 4(d), and the average loss is 6.4 dB. These results demonstrate that the proposed topological network is capable of performing matrix computations while ensuring the successful transmission of light energy.
Finally, the stability of the system in response to temperature changes was also evaluated. In Fig. 4(e), after each temperature change, CF can revert to larger than 0.99 within 30 iterations. This demonstrates that the chip can operate stably even when the external environment undergoes significant changes over a range of more than 10 °C.
By introducing an additional output port as a reference and computing the final output as the subtraction of energy from other ports with that of the reference port, the application of our structure can be extended to real-valued matrix computation. MZIs, based on transfer matrix, have the ability to perform complex-valued matrix computation. If a beam-splitting structure is integrated onto the chip [42–44], or if part of the topological network is used to obtain multiple coherent optical inputs [30], the chip will have the potential for complex-valued matrix computation.
3.2 Optical routing
Optical routing, as an extension of positive real-valued matrix computation, shares the same principle and experimental equipment. The main difference lies in the matrix T used for configuration. For optical routing, T is set as a permutation matrix based on the desired routing goal. As shown in Fig. 5, light enters the chip through input ports and can be routed to any desired output ports. We linearly scale the column vectors of T to ensure the maximum element of each column is equal to 1. Additionally, the extinction ratio, which measures the difference in optical energy between the target output port and the other output ports, is calculated. The extinction ratio is greater than 11.5 dB, and the average extinction ratio is about 20 dB. The above results show that the proposed system can realize high quality optical routing.
3.3 Low-loss optical energy splitting
In the training process of this function, only one single wavelength of light is input from one port. It is necessary to consider both the proportional relationship between the optical power of each output port and the total output power. The formula for calculating CF is shown in Eq. (3).
Fig. 6. Training results of low-loss energy splitting. Light blue columns indicate the target splitting ratio, and dark blue columns represent the energy ratio of each output port after normalizing the total optical power to 1.
4. Discussion
The current quadrilateral topological network can also be extended by increasing the number of MZI to achieve higher order matrix multiplication. As the network scale grows, additional optical transmission paths become available, leading to increased complexity in chip training and a slower convergence of CF. However, considering the difficulty of TBU state monitoring and the fabrication error of MZIs, treating the chip as a black box is more suitable for large-scale topological networks. Moreover, very large-scale chips can also be considered to add gratings to the structure for monitoring intermediate steps. In this way, the configuration of a large structure can be divided into multiple configurations of small structures, reducing the difficulty of chip training. And to solve the problem of loss, the optical power can be introduced into the calculation of CF, allowing the chip to continuously monitor the output optical power during the self-configuration process, similar to the approach used in this paper for low-loss optical energy splitting. Currently, the chips are fabricated on the SOI platform. In future research, alternative platforms such as silicon nitride (SiN) can be explored to reduce loss resulting from long waveguides in large-scale topological networks [45,46]. Lithium niobate (LN) is also a rapidly developing platform for the manufacture of optical integrated devices in recent years [47,48]. Several MZI projects based on lithium niobate-on-insulator (LNOI) have been reported [49–52]. Leveraging the electro-optical properties of LN, lower π-shift voltages can be achieved, thus reducing the power consumption and improving the reaction speed.
The chip can also find applications in the field of microwave photonics, enabling operations such as temporal integration, temporal differentiation, and temporal Hilbert transformations on microwave signals [8]. This is achieved by utilizing TBUs to create microring or MZI within the topological network. By adjusting the state of TBUs, the bandwidth and extinction ratio of resonant peaks can be modified, allowing for highly flexible system parameters. Furthermore, as the scale of the topological network expands, the cascading and combining of basic devices such as microring and MZI can enable the realization of even more diverse functionalities.
5. Conclusion
In conclusion, we demonstrate a highly reconfigurable quadrilateral MZI network capable of performing positive real-valued matrix computation, optical routing and low-loss light energy splitting. The system can be controlled without knowing the internal structure of the chip. The findings of this work provide a foundation for PICs to realize large-scale programmable networks and open up new application possibilities for integrated optical devices.
Funding
National Natural Science Foundation of China (62075075, 62275088, U21A20511); Innovation Project of Optics Valley Laboratory (OVL2021BG001).
Disclosures
The authors declare no conflicts of interest.
Data Availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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