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Electronic hardware implementations of neural networks

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Abstract

This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom very large scale integrated technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

© 1987 Optical Society of America

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