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Abstract
We developed broadband antireflection structures for millimeter-wave and submillimeter-wave applications, particularly cryogenic applications. The structures were fabricated on silicon using deep reactive ion etching. Three-layer subwavelength structures were fabricated on both sides of a silicon plate with an area of $20 \;{\rm{mm}}^2$. The transmittances of the structures were measured at 28 K. The average transmittance was 97.6% in the frequency range of 200–450 GHz.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. INTRODUCTION
Optical devices that can operate at cryogenic temperatures are required for recent high-sensitivity millimeter-wave and submillimeter-wave observations. One of the technical challenges in the fabrication of such devices is the development of antireflection (AR) coatings that can operate reliably at low temperatures. A common method of creating AR coatings is to coat the surface of an optical substrate with a dielectric material. However, the cracking and delamination of the coating are frequently observed after thermal cycling. This is due to the difference in the coefficient of thermal expansion between the substrate and coating layer. The method of forming subwavelength structures (SWSs) [1–4] on the surface of optical components is expected to be a reliable AR technology under cryogenic conditions. This prevents the problems associated with thermal expansion because AR layers are made of the same material as the substrate.
Various methods have been proposed for the fabrication of SWSs for millimeter-wave and submillimeter-wave applications (e.g., direct machining [5–9], laser ablation [7,10–13], and dry etching [14–20]). Dry etching allows for highly controllable processing at a small scale, which is not possible with other methods. This method allows us to fabricate micrometer-scale structures with aspect ratios of 50:1 or higher. It enables high-frequency and broadband AR coating with high transmittance, which cannot be achieved by other methods. This technology is expected to improve the optical efficiency and bandwidth of millimeter-wave and submillimeter-wave optical systems. Two- and three-layer SWSs using dry etching were reported by Defrance et al. [18] and Makitsubo et al. [16], respectively. They fabricated each SWS layer on a silicon wafer independently and then bonded them. In this paper, we report a method for fabricating three-layer SWSs on a single silicon wafer using dry etching. The proposed method is simpler than other multilayer SWS fabrication processes using dry etching in previous studies. The technology presented in this paper has a wide range of applications—from silicon vacuum windows to cryostat filters for broadband astronomical observations.
2. SWS DESIGN
The AR principle in SWS involves manipulating the density of the medium to tune its effective refractive index (${n_{{\rm{eff}}}}$). The relation between the refractive index and density of a microinhomogeneous medium is known as Clausius–Mossotti and Maxwell Garnett relations [21]. The AR design presented in this paper was obtained using the Chebyshev transformers [22]. The Chebyshev transformer provides a passband transmittance with equal ripples. The in-band frequency is determined by the central frequency of the band, number of layers, and maximum magnitude of reflection coefficient ${\Gamma _m}$. Figure 1 shows the calculated transmittances of AR-coated silicon designed by the Chebyshev transformer theory using different numbers of layers. Here, we assumed a central band frequency at 307 GHz and ${\Gamma _m} = 0.08$. The three-layer Chebyshev transformers using these conditions gives $n1 = 2.68$, $n2 = 1.84$, and $n3 = 1.27$, where $n1$, $n2$, and $n3$ are the effective indices of the first, second, and third layers in order of the substrate ($n = 3.4$) to vacuum ($n = 1$), respectively. To realize this three-layer AR coating with SWSs, we investigated the relationship between ${n_{{\rm{eff}}}}$ and the silicon filling rate through electromagnetic simulation using the Ansys HFSS. We then compared the transmittance spectra of the dielectric medium and $2 \times 2$ squared SWSs on silicon in the frequency range of 100–500 GHz. The simulation model to validate ${n_{{\rm{eff}}}}$ of SWSs is shown in Fig. 2(a). Moreover, the design of the three-layer SWS based on the Chebyshev transformer theory is shown in Fig. 2(b). The structures are arranged in a $180\,\,\unicode{x00B5}{\rm m}$ pitch lattice. The relationship between ${n_{{\rm{eff}}}}$ and trench width $w$ in the AR layer is shown in Fig. 3. The design parameters of the three-layer SWS are listed in Table 1.
Fig. 1. Calculated transmittances of AR-coated silicon designed by the Chebyshev transformers. Absorption was neglected and both sides of silicon were coated. The transmittance of native silicon is also shown as a reference. We assumed that the thickness of the silicon substrate is 1 mm.
Fig. 2. (a) Simulation model to validate ${n_{{\rm{eff}}}}$ of SWSs with $p = 180\,\,\unicode{x00B5}{\rm m}$. (b) Schematic of the three-layer SWS and the definition of design parameters.
Fig. 3. Relationship between ${n_{{\rm{eff}}}}$ and $w$. The blue curve is the polynomial fitting function. The dashed horizontal lines indicate the refractive indices of the AR layers derived by the Chebyshev transformer theory. The dashed vertical lines represent the designed trench widths of the AR layers defined in Fig. 2(b).
3. FABRICATION
The three-layer SWSs were fabricated on a 1 mm thick silicon substrate with an area of $35 \;{\rm{mm}}^2$. This process is shown in Fig. 4. The lattice patterns of the first, second, and third layers were printed on a photoresist mask, aluminum (Al) mask, and silicon dioxide (${\rm{Si}}{{\rm{O}}_2}$) mask, respectively. The ${\rm{Si}}{{\rm{O}}_2}$ mask was etched with buffered hydrogen fluoride, and the Al and photoresist masks were etched with tetramethylammonium hydroxide (TMAH).
Deep reactive ion etching (DRIE) [23] was employed to etch the silicon. DRIE consists of three processes: passivation, bottom etching, and isotopic etching. The passivation process covers the sidewalls and bottom of a trench with ${{\rm{C}}_4}{{\rm{F}}_8}$ gas. In the bottom etching process, ${{\rm{SF}}_6}$ plasma is then accelerated toward the bottom of the trench, and the passivated bottom surface is selectively etched. In the isotopic etching process, only the bottom of the trench is etched because the sidewalls are still passivated. DRIE was performed using SPTS MUC-21 ASE-Pegasus. After the first layer was etched to the desired depth, the photoresist mask was removed by ${{\rm{O}}_2}$ plasma ashing. In the next step, the first and second layers were etched simultaneously. When the second layer was etched to the desired depth, the Al mask was removed using TMAH. After the etching of the third layer was completed, the three-layer structures were obtained. In addition, the surface was cleaned by gas irradiation with ${{\rm{O}}_2}$ and ${{\rm{CF}}_4}$.
To achieve high transmittance, SWSs should be fabricated on both sides of the silicon substrate. Therefore, we prepared two silicon samples with SWSs formed on one side and joined them by bonding the other sides. The unmachined surfaces of the samples were polished by chemical mechanical polishing and bonded by activating them with a fast atom beam. To ensure that the fabrication of SWSs on the two surfaces was operated under identical conditions, we fabricated the SWS on the two native samples independently and then bonded them back-to-back.
The ${{\rm{C}}_4}{{\rm{F}}_8}$ gas used in the passivation process was deposited at the edge of the step structures. As a result, spikes of residual silicon were found at the edges, as shown in Fig. 5(a). To remove these spikes, ${{\rm{O}}_2}$ plasma ashing was periodically applied during the DRIE process. The structures with the spikes removed after ${{\rm{O}}_2}$ plasma ashing are shown in Fig. 5(b).
Fig. 5. Cross sections of the SWSs (a) without ${{\rm{O}}_2}$ ashing and (b) with ${{\rm{O}}_2}$ ashing.
The depths of the trenches, $d1$, $d2$, and $d3$, were determined according to the relationship between the number of DRIE cycles and machining depth. These relationships were estimated using a number of test samples. A comparison between the estimated and measured depths at the center of the final sample is shown in Fig. 6. These measured depths are in agreement with the predicted values, indicating that the depth of each layer can be controlled as expected.
Fig. 6. Relationship between the number of DRIE cycles and the depths of the trenches. The dashed curves are the predicted values, and the dots are the values at the center of one side measured by a laser microscope. In the cases of $d1$ and $d2$, the etched depths per DRIE cycle were changed during the process because the etching areas were changed when associated with the number of etched layers. The red vertical line indicates the timing of the 3 min ${{\rm{O}}_2}$ ashing applied before the DRIE process.
The relationship between the widths of the trenches and the number of DRIE cycles is shown in Fig. 7. The phenomenon in which the processed width becomes wider than the mask design is referred to as “undercutting.” We let undercutting occur and adjusted the final widths using a mask design with narrower widths.
Fig. 7. Relationship between the number of DRIE cycles and trench widths. The dots represent the values measured at the center of the sample. The dashed horizontal lines indicate the design values.
A scanning electron microscope (SEM) image of the SWSs fabricated on silicon is shown in Fig. 8. The fabrication procedure presented in this paper can be implemented to the multilayer AR design, in which the refractive indices are successively increasing from vacuum to substrate.
4. SHAPE MEASUREMENT
The shapes of the SWSs on both sides of the sample were determined using a laser microscope. There were 13 sampling points on each side. Each sampling point contained $4 \times 3$ three-layer structures. The distributions of the design parameters measured at the thirteen points are shown in Fig. 9. We denote the sides of the silicon sample as surfaces 1 and 2. Table 2 summarizes the mean values of the parameters measured over the entire sample area. The values measured at the center position are also presented. Errors are expressed as standard deviations.
Table 1. Design Parameters of the Three-Layer SWS
Table 2. Mean Values of the Design Parameters and Their Errors with Standard Deviations
5. TRANSMITTANCE MEASUREMENT
The transmittance measurement setup is shown in Fig. 10. A Fourier transform spectrometer (FTS) was used to measure the transmittance of the sample at cryogenic temperatures. White light emitted from the mercury lamp was split and combined by the wire grid polarizer. The optical length of a split path can be changed by the linear stage under the rooftop mirror. The linear polarizers were placed in front of the mercury lamp and detector. The sample was cut into a square with an area of $20 \;{\rm{mm}}^2$ to be mounted on a wheel-shaped holder in a dewar. An aperture with a diameter of 6 mm was placed behind the sample. The transmittance of the sample was measured by comparing the detector signals with and without the sample. The configuration was changed by rotating the wheel holder. The linear-polarized light emitted from the FTS entered the dewar through a plastic window. The light that passed through the aperture was focused by a Winston cone and detected by an InSb bolometer installed in the dewar.
Fig. 10. (a) Schematic of the transmittance measurement setup. (b) Photograph of the wheel-shaped sample holder. There is an aperture with a diameter of 6 mm on the left side of the wheel; this aperture is used for reference measurements. The sample is pasted on the lower part of the wheel. Another aperture with the same diameter is placed behind the sample. The other sample on the right is a spare sample, and it is not used for this measurement. (c) Photograph of the measurement setup with the dewar and FTS.
The measured transmittances are shown in Fig. 11. The transmittances obtained using the design parameters shown in Tables 1 and 2 are also shown. These transmittances were calculated using Ansys HFSS. In the simulations, we assumed the refractive index and loss tangent of silicon as 3.4 and $2.0 \times {10^{- 4}}$, respectively [24]. The measurement data show an average transmittance of 97.6% in the frequency range of 200–450 GHz, and this is consistent with the average transmittance of designed structures at 97.8%.
Fig. 11. Transmittance of the silicon plate with three-layer SWSs on both sides. The blue curve is the simulation result obtained using the parameters listed in Table 1. The green and yellow curves are the simulation results obtained using the parameters listed in Table 2 for the “entire area” and “center,” respectively. The measured bandwidth and transmittance are consistent with the calculations. There is a slight discrepancy in the transmittance between measurement and calculations. We suppose that this came from the nonuniformity of the structures. The black dots are the measurement data obtained at 28 K.
6. DISCUSSION
We established a method to fabricate multilayer SWSs on a single silicon wafer with desired depths and widths. Only the central part of the silicon sample was useful for transmittance measurement because the incident light was truncated at an aperture with a diameter of 6 mm. Therefore, we adjusted the fabrication process so that the structure of the central part matched the designed structure. However, as shown in Fig. 9, there was nonuniformity in the parameters of the structure. In addition, the depths and widths of the trenches increased with the distance from the center. In actual millimeter-wave and submillimeter-wave observations, most parts of the surface of an optical device are expected to be illuminated. Therefore, the nonuniformity of the SWSs may degrade the optical performance. Therefore, for using large optical devices, it is necessary to investigate the prediction of the expected performance while considering nonuniformity or the mitigation of nonuniformity by improving the fabrication process.
The techniques presented in this paper can be applied to large silicon plates, and, in principle, the allowable size is limited by the process machines. The DRIE process time for a single sample was approximately 5 h, including rapid shape measurements every 25 DRIE cycles. Once the process conditions are fixed, the process time will be reduced to approximately 2 h. A similar process time is expected for fabricating silicon plates of any size. The bandwidth and transmittance of the silicon plates can be improved by increasing the number of SWS layers.
7. CONCLUSIONS
Three-layer SWSs were fabricated on a silicon plate with an area of $20 \;{\rm{mm}}^2$ using DRIE. The depth and width of each layer were controlled on the basis of the relationship between the design parameters and number of DRIE cycles. The spikes of residual silicon were removed by introducing ${{\rm{O}}_2}$ plasma ashing to the DRIE process.
A silicon plate with SWSs on both sides was fabricated by bonding two silicon samples with SWSs on one side through fast atom beam irradiation. The transmittance of the silicon sample was measured at 28 K. The average transmittance was 97.6% in the frequency range of 200–450 GHz, and this is consistent with the average transmittance of designed structures of 97.8%.
Funding
Japan Society for the Promotion of Science (17H01115); National Astronomical Observatory of Japan (2001-0102).
Acknowledgment
We thank Makoto Mita, Kumi Ishikawa, and Yuichiro Ezoe for their advice on the DRIE techniques. We also thank Takehiko Wada for his technical advice on wafer bonding and Ryota Takaku for advice on the shape measurement technique. Chemical polishing and wafer bonding were performed by D-Process Inc. We thank Editage (www.editage.com) for English language editing.
Disclosures
The authors declare no conflicts of interest.
Data Availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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