Abstract
3D simulations are conducted using Lumerical software to study the performance of surface illuminated silicon positive–intrinsic–negative photodiodes with microholes. Drift-diffusion equations are solved including the effects of carrier lifetime due to Shockley–Read–Hall and Auger recombination mechanisms, as well as high field mobility. Lumerical’s FDTD tool is used to determine the light absorption in the device. The generation profile is imported to Lumerical’s CHARGE tool to determine the transient-limited impulse response. An equivalent circuit of the photodiode with microholes is developed for the simulation of an end-to-end high-speed system. Simulation results show an open eye diagram at 50 Gbps for $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ devices.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
Corrections
18 August 2023: A correction was made to the Acknowledgment.
1. INTRODUCTION
Industry reports state that the annual growth rate of global Internet traffic was approximately 30% between 2018 and 2022 [1]. This significant growth has been driven by several factors such as the increased number of connected devices and the rapid adoption of cloud computing. These same reports predict that the growth in data traffic will continue as broadband speeds keep increasing. This growth, however, creates a strain on network infrastructure, and drives the need for low-cost, high-speed, and energy-efficient optical interconnects inside datacenters.
Currently, high-speed optical intra-datacenter interconnects use short-reach multimode fiber (MMF) links with vertical cavity surface emitting lasers (VCSELs) and positive–intrinsic–negative (PIN) photodiodes (PDs). In these links, complementary metal–oxide–semiconductor (CMOS) transimpedance amplifiers (TIAs) are commonly used with PDs that are fabricated using column III-V materials, such as GaAs and InGaAs. The incompatibility of the latter materials with the CMOS process dictates that the fabrication and wire bonding processes of the TIAs and PDs be carried out separately, which incurs additional cost during mass production. Furthermore, sub-optimal packaging usually leads to unwanted parasitic inductance and capacitance, which can hinder the performance of high-speed devices and lead to electrical cross talk. A discussion of the performance limits of GaAs PDs can be found in [2].
On the other hand, silicon PDs (SiPDs) offer high sensitivity, low noise, low dark current, and large bandwidth. Their CMOS compatibility and monolithic integration with TIAs makes them more cost effective. Commercial planar SiPDs that can operate at 1.25 Gbps have been reported [3]. Planar SiPDs are limited by the trade-off that exists between high-speed operation and high quantum efficiency. High-speed operation typically requires the SiPD to have a thin absorber layer, which reduces quantum efficiency due to the limited absorption of the incident photons. Increasing the absorber thickness improves the quantum efficiency of the SiPD at the expense of increasing the transit time of the charge carriers, which, in turn, limits the speed of the device [4].
To address the limitations of SiPDs, novel structural enhancements were investigated in the literature such as including photon-trapping microholes in surface-illuminated SiPDs and Ge-on-Si PDs [4–11]. The use of microholes improves the absorption efficiency of the intrinsic $i$ layer and the overall efficiency of the PD, while maintaining a fast device response. Microholes also reduce the capacitance by removing material, which, in turn, helps in high-speed performance. High-speed performance evaluation of surface illuminated PIN PDs by solving the 1D carrier transport drift-diffusion equations has been conducted on planar SiPDs in [12] and on InGaAs PDs in [13]. The dielectric relaxation’s impact on the displacement current and PD response time in semiconductor PDs has been discussed using a 1D model [14]. In [15], the authors used both 1D and 2D simulations to solve carrier transport equations to assess the PIN diode nonlinearity performance. Several 2D studies of image sensors with gratings were conducted using Lumerical’s CHARGE tool [16]. In this study, 3D modeling and simulations are used to solve the carrier transport drift-diffusion equations for surface illuminated PIN PDs with microholes. For such devices, 1D and 2D modelings are not adequate to fully characterize the structure behavior. To the best of our knowledge, no 3D simulations have been carried out on this topic. The studied structures are simulated using Lumerical’s FDTD and CHARGE tools. The Shockley–Read–Hall (SRH) and Auger models for carrier lifetime, and the saturation model for carrier mobility are chosen and validated with the literature experimental data. The generation of electron–hole pairs due to a normally incident plane wave that illuminates the top surface of the PD is evaluated using Lumerical’s FDTD tool. Devices with and without a microhole are compared through a DC analysis and the transient impulse responses at ${-}3\;{\rm V} $ bias. In addition, an AC small-signal (SSAC) analysis is carried out to evaluate the junction capacitance of the SiPD with a single microhole. To model larger devices, such as those with arrayed microholes, the junction capacitance for a single-microhole device is scaled, and the corresponding junction capacitance is estimated. The equivalent circuit of the SiPD is derived and included in a full optical link simulation model to evaluate the high-speed performance of the PD. The eye diagrams for a transmitter-receiver (TX-RX) system operated at different bit rates and using different SiPD structure sizes are generated.
2. PHOTODIODE MODEL
A. Device Structure
The studied structure consists of a planar SiPD as shown in Fig. 1(a). A lightly doped $i$ layer with 2 µm thickness is sandwiched between highly doped $p$ and $n$ layers [4,5]. The abrupt doping type is used, and the doping concentrations are presented in Table 1. The layers are positioned on top of a silicon oxide glass substrate. This structure is referred to as a $4\,\,\unicode{x00B5}{\rm m} \times 4\,\,\unicode{x00B5}{\rm m}$ single-microhole device. Throughout this study, an $({x_0}\,\unicode{x00B5}{\rm m} \times {y_0}\,\unicode{x00B5}{\rm m})$ device refers to a structure where the width of the $i$ and $p$ layers is ${x_0}\,\unicode{x00B5}{\rm m}$ along the $x$ axis, and their length is ${y_0}\,\unicode{x00B5}{\rm m}$ along the $y$ axis. A square microhole filled with air is etched at the top surface going through the $p$ and $i$ layers and just reaching the $n$ layer, as shown in Fig. 1(b). This microhole, whose size is $0.7\,\,\unicode{x00B5}{\rm m} \times 0.7\,\,\unicode{x00B5}{\rm m}$, serves as a photon-trapping medium.
B. Drift-Diffusion Equations Model
PD generation, recombination, and transport phenomena are described by drift-diffusion equations, continuity equations, and the Poisson equation. In all subsequent equations, the $n$ subscript denotes electrons and the $p$ subscript denotes holes. The drift-diffusion equations are:
Here, ${{\textbf J}_{n,p}}$ is the current density, ${\textbf E}$ is the electrostatic field, $n$ and $p$ are carrier concentrations, $q$ is the electron charge, ${D_{n,p}}$ is the carrier diffusion, and ${\mu ^\prime _{n,p}}$ is the carrier mobility.The total current density is given by
where the displacement current density ${{\textbf J}_d}$ is given byThe continuity equations are given by
Here, $G$ and $R$ are the charge carrier generation and recombination rate, respectively.The Poisson equation is given by
where ${N_D}$ and ${N_A}$ are respective concentrations of the donor and acceptor impurities.In our model, both SRH and Auger recombinations are considered. The SRH recombination rate is described by the following equation:
where ${n_i}$ is the intrinsic carrier density, and ${n_1}$ and ${p_1}$ are the effective densities of carriers in the trap states, which are given by where ${k_B}$ is the Boltzmann constant, $T$ is the absolute temperature, and ${E_t}$, ${E_i}$ are the trap state energy and intrinsic energy, respectively. The Fossum model is adopted to calculate the carrier lifetimes for SRH recombinations:The Auger recombination rate is given by
where ${C_n} = 2.8 \times {10^{- 31}}$ and ${C_p} = 9.9 \times {10^{- 32}}$ are the capture rate coefficients for silicon at $300\; {\rm K}$ [18]. The corresponding Auger carrier lifetimes are used from [18], and the overall carrier lifetimes are given byIn this study, the Caughey–Thomas carrier mobility model is considered. The mobility described by this model takes into consideration the effects of the doping concentration as well as the lattice and impurity scattering effects. In the Caughey–Thomas model, the carrier mobilities are given by
C. FDTD Simulation Model
Lumerical’s FDTD tool was used to study the device absorption at the wavelength ${\lambda _0} = 850\;{\rm nm} $. The simulated device has the same structure shown in Fig. 1 without the metal contacts [21]. The numerical solution assumed periodic boundary conditions in the $x \text{-} y$ plane and a perfectly matched layer at the top and bottom planes. The optical source, illuminating the top surface of the device, emits a monochromatic optical plane wave pulse. The electric field component of this optical wave is polarized in the $x$ direction and is given by
Assuming that each absorbed photon excites a single electron–hole pair, the generation rate is equivalent to the photon absorption rate and can be written as
D. Simulations Setup
The simulations were conducted using Lumerical’s 3D solvers of CHARGE and FDTD tools, Release 2022 R1. A workstation running 64-bit Microsoft Windows-10 on a 4 GHz Intel Core i7-6700K CPU with four cores and eight threads was used. The workstation has 64 GB of RAM, 1 TB SSD, and an Nvidia GeForce GTX980Ti GPU. The approximate durations needed to run the steady-state DC regime, transient, and SSAC simulations for a single-microhole device are shown in Table 4. The time step used is 400 fs, and the minimum spatial mesh size is around 50 nm.
Transient 3D simulations of large-sized devices, such as those ranging from $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ to $100\,\,\unicode{x00B5}{\rm m} \times 100\,\,\unicode{x00B5}{\rm m}$, require substantial run times and computing resources. Therefore, in Section 4.A, a methodology for scaling the parameters of such devices is detailed, based on the transient impulse response and the junction capacitance obtained, both from the single-microhole device.
3. DC AND TRANSIENT RESULTS
A. DC Results
Steady-state DC simulations were carried out to assess the electrostatic characteristics of the bulk device and single-microhole device under a dark condition. The current–voltage (I-V) curves for the anode and cathode, obtained at a range of bias voltages, are presented in Fig. 4. These currents represent the total dark current. The results of the anode and cathode currents for the single-microhole device exhibit excellent agreement at forward bias, but at reverse bias, a small deviation is observed due to some numerical instabilities in CHARGE. To ensure the reliability of the results, the simulations were continuously tested under varied parameters. Despite these efforts, some variation in the values of the cathode and anode currents persisted at low-current values [22]. The current at the anode, or at the cathode, of the single-microhole device agrees with the respective current of the bulk device regardless of the bias. Figure 5(a) shows the electrostatic field distribution in the cross section cutting through the microhole. The large electrostatic field values can be attributed to the local charge accumulation near the edges.
The current density results are depicted in Fig. 6, where the highest values are reported near the cathodes region. To investigate the impact of the surface recombination velocity on the current density profile, the simulation results obtained with different values of this parameter at the Si/air interface were compared. Figure 6(b) illustrates the effect of a drastically increased surface recombination velocity 0.1 cm/s, which leads to an increase in the current density at the hole boundaries due to the enhanced surface recombination effect.
B. Transient Results
The transit time-limited bandwidth is given by the following equation [6]:
where ${T_r}$ is the transit time, $v_n^S$ is the electron saturation velocity, and ${W_i}$ is the $i$ layer thickness. Based on this equation, the theoretical bandwidth is about 22 GHz. To evaluate the 3 dB bandwidth of the studied devices, the transient impulse response is extracted for both the single-microhole device and bulk device over a time window of 250 ps, at ${-}{3}\;{\rm V}$, which is the typical supply voltage used in datacenter optical transceivers. The optical generation used in this case is imported from FDTD (Fig. 3) and scaled with a factor of ${10^9}$ to achieve an incident power of 0 dBm, which is the typical value for datacenter transceivers. The normalized currents from the anode and cathode for the single-microhole device and bulk device are depicted in Figs. 7(a) and 7(b), respectively. The disagreement between the anode and cathode currents continues to be present in the transient impulse response results.The electron current, hole current, and displacement current for the single-microhole device are shown in Fig. 8. The hole current ${I_p}$ was found to dominate the total anode current. Due to the issue of inequality of cathode and anode currents, the average current is used in all of the upcoming simulations and 3 dB bandwidth calculations. Moreover, all the impulses are extended by padding the value at 250–2000 ps to study the tail effect. The average transit time-limited 3 dB bandwidth for the single-microhole device, presented in Table 5, is about 10.6 GHz, which is lower than the aforementioned theoretical bandwidth. To further investigate this issue, a 2D simulation of the bulk device was carried out at a higher bias voltage ${-}10\;{\rm V} $ with the same FDTD generation [Fig. 3(a)] and with the same ${10^9}$ scaling factor. This 2D simulation yielded a 3 dB bandwidth of about 17.7 GHz, as shown in Table 5, which is close to the theoretical value. It is worth noting that our repeated attempts to obtain results for 3D simulations at ${-}10\;{\rm V} $ bias resulted in a diverging numerical solution.
In addition, the single-microhole structure’s impulse response under uniform generation was investigated in 3D. A uniform generation with the value of ${10^{32}}\; {{\rm m}^{- 3}} \cdot {{\rm s}^{- 1}}$ limited to the $i$ layer of the structure, as shown in Fig. 9(a), was created in MATLAB and imported to the CHARGE solver. The impulse response from both contacts is plotted in Fig. 9(b). The results demonstrate that the impulse response is not affected by the $p$ or $n$ layer absorption, and that the $i$ layer is the primary contributor to the resulting current. An improvement in the 3 dB bandwidth of about 2.6 GHz, from 10.6 to 13.2 GHz, is noticed.
4. FULL OPTICAL LINK RESULTS
A. Small Signal Results and Scaling
A small signal analysis is carried out using the CHARGE tool to evaluate the junction capacitance of different structures at a voltage of ${-}3\;{\rm V} $ and frequency of 1 MHz. The junction capacitance is one of the key parameters that defines the 3 dB bandwidth of the PD. Therefore, reducing the junction capacitance is crucial to improve the PD high-frequency response and increase its bandwidth. PIN PDs can be regarded as a parallel-plate capacitor whose capacitance is defined by
where $A$ is the area of the device junction, and ${W_i}$ is the width of the $i$ layer. The introduction of microholes, with area ${A_h}$, in the $p$ and $i$ layers of the PD reduces the junction area and thus lowers the junction capacitance. To take this into account, a filling factor is added to Eq. (21), as presented in [6]. The filling factor, ${\rho _f}$, is defined by Consequently, the junction capacitance for a device with a microhole becomes The simulation was carried for the single-microhole device as well as for a larger device that has a $2 \times 2$ array of microholes. The arrayed device size and microhole centerline spacing along with the respective junction capacitance values are presented in Tables 6 and 7.The larger devices were scaled based on the assumption that the filling factor would remain constant when moving from small single-microhole devices to larger devices with more microholes. Therefore, for a scaled junction capacitance of a device of size ($x\;\unicode{x00B5}{\rm m}\times y\;\unicode{x00B5}{\rm m}$), the previous equation can be rewritten in terms of the single-microhole device’s junction capacitance. The resulting capacitances of such devices are presented in Table 7. The scaled junction capacitance is used for analysis of the impulse response and optical link performance of bigger devices.
B. Optical Link Analysis
The transient time-limited bandwidth, calculated in Section 3 for a device with a single microhole, is assumed to be the same for devices with a large number of microholes. The bandwidth of the PD is composed of the transit time-limited impulse response and the PD equivalent circuit that we will present in this section.
The equivalent circuit model of the PD, presented in Fig. 10(a), incorporates the junction capacitance ${C_j}$, a bonding capacitance of ${C_b} = 150\;{\rm fF}$, and a series resistance ${R_s} = 83\; \Omega$ [4]. The load resistance ${R_L}$ was set to $50 \;\Omega$. The PD performance was tested using a full optical link as shown in Fig. 10(b). The transmitter consists of a pseudo random bit sequence (PRBS) generator of 4000 bits, a pulse-shaping Gaussian filter with 12 ps rise time, and a VCSEL source with a 3 dB bandwidth of 25 GHz. At the receiver side, the output was convolved with the impulse response of the PD. A TIA amplifier, with a 3 dB bandwidth equal to 75% of the bit rate, was used to convert the small electrical current generated by the SiPD into a voltage signal with sufficient gain and low noise [4]. The impulse response of bigger-sized devices ranging from $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ to $100\,\,\unicode{x00B5}{\rm m} \times 100\,\,\unicode{x00B5}{\rm m}$ was evaluated based on the proper scaling of the junction capacitance of each device size, as described in Section 4.A. The length of the SiPD impulse response used throughout this section for the eye diagram simulations is 2000 ps. The results at a bias voltage of ${-}3\;{\rm V} $ are shown in Fig. 11.
In addition, the performance of various PD sizes was evaluated by conducting eye diagrams at different bit rates. Specifically, the full TX-RX system eye diagrams operated at 25 and 5 Gbps are plotted for different device structures with a tail effect, by extending all the impulse responses in the PD model to 2000 ps. Results show that the $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ and $30\,\,\unicode{x00B5}{\rm m} \times 30\,\,\unicode{x00B5}{\rm m}$ devices exhibit good eye opening at 25 Gbps, as evidenced by the eye diagrams shown in Figs. 12(a) and 12(b), respectively. However, the $50\,\,\unicode{x00B5}{\rm m} \times 50\,\,\unicode{x00B5}{\rm m}$ device displayed a distorted eye diagram, as depicted in Fig. 12(c). Interestingly, it was observed that reducing the bit rate to 5 Gbps led to a good eye opening for the $100\,\,\unicode{x00B5}{\rm m} \times 100\,\,\unicode{x00B5}{\rm m}$ device, as shown in Fig. 12(d).
Furthermore, the operation of the $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ device at a high bit rate of 50 Gbps was investigated. To this end, the bonding capacitance was set to ${C_b} = 150\;{\rm fF}$ and the series resistance to ${R_s} = 83 \Omega$, while the pattern generator rise time was set to 6 ps and the 3 dB bandwidth of the VCSEL was set to 50 GHz. As seen in Fig. 13(a), the signal experienced heavy distortion under these conditions. The filling factor used in this case is ${\rho _f} = 0.03$.
To reduce the junction capacitance of the device and improve its bandwidth, a larger filling factor of ${\rho _f} = 0.5$ was used for the same $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ device, and with the same values of the bonding capacitance and series resistance, i.e., with ${C_b} = 150\;{\rm fF}$ and ${R_s} = 83\; \Omega$. The results in Fig. 13(b) show that using this filling factor improves the eye diagram’s opening slightly. However, reducing the bonding capacitance to ${C_b} = 70\;{\rm fF}$ and lowering the series resistance to ${R_s} = 3.61\; \Omega$, as suggested in [23], resulted in a more open eye diagram, as shown in Fig. 13(c). This finding highlights the possibility of operating $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ PDs at a bit rate as high as 50 Gbps.
5. CONCLUSION
The performance of PIN SiPDs with a single photon-trapping microhole was investigated through 3D device simulations using FDTD and CHARGE tools from Lumerical. The study was extended to large-sized devices containing an array of microholes. The 3D simulations at ${-}3\;{\rm V} $ bias voltage resulted in an average 3 dB bandwidth of about 10.6 GHz with a slight mismatch between the anode and cathode currents. The findings of this study suggest that the observed issues in the 3D simulations may be due to numerical instabilities. The detailed approach of capacitance scaling allowed the end-to-end link analysis for several structure sizes. The eye diagrams for a receiver system based on the impulse response of such SiPDs were analyzed. The study considered a $100\,\,\unicode{x00B5}{\rm m} \times 100\,\,\unicode{x00B5}{\rm m}$ devices at the bit rate of 5 Gbps; device sizes of $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$, $30\,\,\unicode{x00B5}{\rm m} \times 30\,\,\unicode{x00B5}{\rm m}$, and $50\,\,\unicode{x00B5}{\rm m} \times 50\,\,\unicode{x00B5}{\rm m}$ at the bit rate of 25 Gbps; and devices of $20\,\,\unicode{x00B5}{\rm m} \times 20\,\,\unicode{x00B5}{\rm m}$ at the bit rate of 50 Gbps. The latter revealed the possibility of operating the device at a low bonding capacitance and low series resistance. These findings can be informative in the design and optimization of PD structures for high-speed optical communication systems for datacenters.
Funding
American University of Sharjah (FRG21-M-E66, FRG-S23-E04).
Acknowledgment
The work in this paper was supported, in part, by the Open Access Program from the American University of Sharjah. This paper represents the opinions of the author(s) and does not mean to represent the position or opinions of the American University of Sharjah. The authors acknowledge the support of the Office of Research and Graduate Studies at the American University of Sharjah as well as the support of W&Wsens Devices, Inc.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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