Abstract
This paper presents a global proposal and methodology for developing
digital printed electronics (PE) prototypes, circuits and application
specific printed electronics circuits (ASPECs). We start from a circuit
specification using standard Hardware Description Languages (HDL)
and executing its functional simulation. Then we perform logic synthesis
that includes logic gate minimization by applying state-of-the-art
algorithms embedded in our proposed electronic design automation (EDA)
tools to minimize the number of transistors required to implement
the circuit. Later technology mapping is applied, taking into account
the available technology, (i.e., PMOS only technologies) and the cell
design style (either Standard Cells or Inkjet Gate Array). These layout
strategies are equivalent to those available in application specific
integrated circuits (ASICs) flows but adapting them to Printed Electronics,
which vary greatly depending on the targeted technology. Then Place
& Route tools perform floorplan, placement and wiring of cells,
which will be checked by the corresponding layout versus schematic
(LVS). Afterwards we execute an electrical simulation including parasitic
capacitances and relevant parameters. Finally, we obtain the prototypes
which will be characterized and tested. The most important aspect
of the proposed methodology is that it is portable to different PE
processes, so that considerations and variations between different
fabrication processes do not affect the validity of our approach.
As final results, we present fabricated prototypes that are currently
being characterized and tested.
© 2015 IEEE
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