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Optica Publishing Group
  • Journal of Display Technology
  • Vol. 11,
  • Issue 9,
  • pp. 720-724
  • (2015)

Analyses of Surface and Interfacial Layers in Polycrystalline ${Cu}_{2}{O}$ Thin-Film Transistors

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Abstract

Effects of low temperature $({{300}}^{\circ}{C})$ annealing on ${Cu}_{2}{O}$ films were investigated by analyzing the film stacking structures with photoemission spectroscopy, X-ray reflectivity spectroscopy and spectroscopic ellipsometory in relation to $p$ -channel TFT characteristics and possible origins of trap states. The Hall mobility of optimum ${Cu}_{2}{O}$ films was ${{2.1}}~{cm}^{2}/({V}{\cdot}{s})$ ; however, the bottom-gate ${Cu}_{2}{O}$ TFT exhibited a much lower field effect mobility of the order of 10 $^{-4}~{cm}^{2}/({V}{\cdot}{s})$ and an on/off drain current ratio of 10 $^{3}$ . This work detected a surface layer and an interface layer in the ${Cu}_{2}{O}/~{SiO}_{2}$ samples, i.e., the surface layer included the $2+$ state of Cu ions that would form subgap hole trap states at the back channel region. In addition, the low-density layer at the ${Cu}_{2}{O}{{--}}{SiO}_{2}$ interface would produce extra interfacial trap states.

© 2015 IEEE

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