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Coherent dimension reduction with integrated photonic circuits exploiting tailored disorder

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Abstract

The number of systems that are investigated for computation in the physical domain has increased substantially in the recent past. Optical and photonic systems have drawn high interest due to their potential for carrying out energy-efficient linear operations and perceived advantages in latency and general computation speed. One of the main challenges remains to scale up integrated photonic designs to integration densities required for meaningful computation, in particular for matrix-vector multiplications. To address upscaling for photonic computing, here we propose an on-chip scheme for dimension reduction of the input data using random scattering. Exploiting tailored disorder allows us to reduce the incoming dimensionality by more than an order of magnitude, which a shallow subsequent network can use to perform image recognition tasks with high accuracy.

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Data is available from the authors upon reasonable request.

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