We propose and simulate all-optical simultaneous half-adder, half-subtracter, and OR logic gate at 40 Gbit/s based on the cascaded sum-and difference-frequency generation (SFG+DFG) using only one periodically poled lithium niobate (PPLN) waveguide. The SFG and DFG processes generate the Borrow and Carry outputs, respectively. The Sum/Difference and OR are obtained by properly combining the outputs from PPLN after SFG+DFG. The eye diagrams, pulse width, quality-factor (Q-factor), extinction ratio (ER), and tunability are calculated and discussed,showing impressive operation performance.
©2007 Optical Society of America
Future high-performance and ultrahigh-speed optical networks may require all-optical signal processing techniques to overcome the speed limitation of electronics and support necessary networking functions. Previously, many schemes have been demonstrated to realize various digital signal processing (AND, NAND, OR, XOR, NXOR, NOR) in the optical domain [1, 2].In particular, all-optical half-adder [3–7] and half-subtracter  have been proposed and verified. The former can be applied to optical packet checksum calculation and binary counters, and the later may see its applications in encryption and decryption of secure network data and dual-direction binary counters. Based on earlier proposals, using two semiconductor laser amplifiers in a loop mirror (SLALOMs) , employing three terahertz optical asymmetric demultiplexers (TOADs) , or utilizing four semiconductor optical amplifiers (SOAs)  can implement the half-adder. These schemes have shown some advantages, however, they suffer from using several components, which greatly increases the system complexity. Recently, periodically poled lithium niobate (PPLN) waveguide is used to perform the AND operation, which corresponds to the Carry of the half-adder [6, 7]. By use of one PPLN and one SOA, the half-adder is successfully realized . Furthermore, simultaneous half-subtracter and half-adder are also implemented with one PPLN and two SOAs . Nevertheless, two or three elements are still needed and the operation speed is limited by the carrier’s recovery time of SOA.
PPLN waveguide has attractive characteristics of ultra-fast response, complete transparency and independence of bit rate and data format, no spontaneous emission noise and no intrinsic frequency chirp. Moreover, various second-order nonlinearities and their cascading can be potentially applied to high speed all-optical signal processing such as wavelength conversions [8–14], AND [6, 7, 15], NOT [16, 17], etc. In this paper, by employing only one PPLN waveguide and exploiting cascaded sum-and difference-frequency generation (SFG+DFG), we propose and simulate, for the first time to our knowledge, simultaneous half-adder, half-subtracter, and OR logic gate at 40 Gbit/s. The operation performance is analyzed, including pulse width, quality-factor (Q-factor), extinction ratio (ER), and tunability.
2. Concept of half-adder, half-subtracter, and OR logic gate
Figure 1 shows a simple digital gate-level conceptual diagram and logical truth table for the half-adder, half-subtracter, and OR logic gate of two independent data streams (A, B). Half-adder contains Sum and Carry, and half-subtracter includes Difference and Borrow. From the truth table, it is noted that the Sum and Difference outputs of half-adder and half-subtracter are identical, corresponding to the XOR between A and B (A⊕B). As the XOR function can be also represented by Ā ∙ B+A ∙ B̄, it may be implemented by using two AND gates with inverters (‘bubbles’) at the input, and an OR gate to combine the outputs Ā∙B and A∙B̄ from AND gates. The Carry output for half-adder is the AND operation (A∙B) which can be simply obtained with a single AND gate. The Borrow output for half-subtracter takes the logical operation in terms of Ā∙B for A-B and A∙B̄ for B-A. Note that Ā∙B and A∙B̄ are realized during the generation of XOR. Additionally, the logical OR of A and B can be expressed as A+Ā∙B or B + A∙B̄, thus it may be achieved by use of an OR gate to combine A and Ā∙ B or B and A∙B̄. As a result, the entire implementation of simultaneous halfadder, half-subtracter, and OR logic gate requires three AND gates, two inverters, and two OR gates.
3. Operation principle
The schematic diagram of the proposed single-PPLN-based simultaneous all-optical halfadder, half-subtracter, and OR logic gate is shown in Fig. 2. In Ref. , the Borrow and Sum/Difference are generated using cross-gain modulation (XGM) in SOAs, and only Carry is carried out by the cascaded second-harmonic generation and difference-frequency generation (SHG+DFG) in the PPLN waveguide. In fact, by exploiting SFG+DFG, it is possible to achieve all above functions with only one PPLN waveguide, which can be briefly explained as follows. Two independent data streams A and B (λSA, λSB), together with the continuous-wave (CW) pump(λP) are launched into the PPLN waveguide, in which the SFG+DFG nonlinear interactions take place under the quasi-phase matching (QPM) condition. In the SFG+DFG processes, the SFG interaction converts one photon from signal A(λSA) and another photon from signal B(λSB) into one sum-frequency photon(λSF), which is simultaneously transformed into one photon of the pump (λP) and the other photon of the new generated idler wave (λi) through the subsequent DFG process. Thus, both signals A and B are depleted during the generation of the sum-frequency and idler waves. Such phenomenon has been successfully observed in our preliminary experimental work [13, 16].For data streams A and B, if the input A data bit is equal to ‘1’, the output B data bit is ‘0’ in spite of input B data bit with any value (‘1’ or ‘0’). The output B data bit is equal to ‘1’ only when input A and B data bits are ‘0’ and ‘1’, respectively. Therefore, the output data stream B takes the logical function of A∙ B (λSB). Similarly, the output data stream A carries the logical result of A ∙ B (λSA). On the other hand, only when both input A and B data bits are ‘1’, the output sum-frequency and idler waves carry the data bit of ‘1’, corresponding to the logical AND of A and B (A∙B).
At the output of the PPLN waveguide, the output Ā∙B (λSB) is combined with input A(λSA) through a coupler acting as an OR gate, because of which A + Ā∙ B is achieved,representing the logical OR of A and B. Meanwhile, by combing A∙B̄(λSA) with input B (λSB), the logical OR can be also obtained as B + A ∙ B̄. Note that the combination of output Ā∙B (λSB) and A∙B̄ (λSA) results in Ā ∙ B + A ∙B̄, i.e. logical XOR corresponding to the Sum/Difference of the half-adder and half-subtracter. The output Ā∙B(λSF or λi) is the Carry of the half-adder. The output Ā∙B(λSB) and A∙B (λSA) are the Borrows of the half-subtracter A-B and B-A, respectively. As shown in Fig. 2, we use tunable filters (TFs) to isolate the required signals, employ variable optical attenuators (VOAs) to equalize the power level of two data streams before entering into the coupler, and utilize tunable delay lines (TDLs) to align the data bits.
4. Results and discussions
The proposed simultaneous half-adder, half-subtracter, and OR logic gate based on SFG+DFG can be described by the following well-known coupled-mode equations under the slowly varying envelope approximation .
where ASA, ASB, ASF, AP and Ai, as functions of the distance z and time t, represent the complex amplitudes of the signal A, signal B, sum-frequency, pump, and idler waves,respectively. β 1j and β 2j are the first and second derivatives of the propagation constant kj with respect to the angular frequency ω, evaluated at ωj (j=SA, SB, SF, P, i). κSFG and κDFG are coupling coefficients for the SFG and DFG processes. deff is the effective nonlinear coefficient. Aeff is the effective interaction area. nj(j = SA, SB, SF, P, i) are the refractive indexes for different optical waves. The parameter μ0 is the permeability and c is the light velocity in vacuum. Δk SFG and Δk DFG refer to the phase mismatching in the SFG and DFG processes, and Λ is the microdomain period of the periodically poled structure in the PPLN waveguide. The above coupled-mode Eqs. (1)-(5) can be numerically solved using the finite difference beam propagation method (FD-BPM) [9, 10].
In the following numerical calculations, two synchronized independent 27-1, 40 Gbit/s pseudorandom bit sequence (PRBS) return-to-zero (RZ) data signals (A, B) with hyperbolicsecant type and 5-ps pulse width are assumed. A continuous-wave pump is considered. The PPLN waveguide is 30 mm long with a waveguide effective area of 50μm2, and its microdomain period is assumed to be 18.8 μm to meet the SFG QPM condition for sumfrequency wavelength at 772.0 nm. The nonlinear coefficient d 33 of the PPLN waveguide is about 27 pm/V and thus the effective nonlinear coefficient (deff = d 33 ∙ 2/π) is approximately 17.2 pm/V. The central wavelengths of signals A and B are set at 1550.0 and 1538.0 nm, respectively, producing the sum-frequency wave at 772.0 nm via SFG. The pump wavelength is tuned at 1555.0 nm, thus the idler wavelength is generated at about 1533.2 nm by DFG. The peak powers of signals A, B and the pump power launched into the PPLN waveguide are assumed to be 1000,1000 ∙ λSA/λSB, and 100 mW, respectively. Similar to the previous theoretical analyses [13, 17], the waveguide propagation loss and amplified spontaneous emission (ASE) background noise are reasonably ignored for simplicity, while the group-velocity mismatch (GVM) and group-velocity dispersion (GVD) are taken into consideration when describing nonlinear interactions between ps-pulses.
Figure 3(a) and Fig. 3(b) show sample 20-bit sequences of two independent input signals A and B, respectively. After SFG+DFG processes, it is found that the half-adder shown in Fig.3(c), Fig. 3(d), and Fig. 3(e), half-subtracter shown in Fig. 3(c), Fig. 3(f), and Fig. 3(g), and OR logic gate shown in Fig. 3(h) and Fig. 3(i) are simultaneously implemented.
Figure 4 plots the eye diagrams for the half-adder, half-subtracter, and OR logic gate. Q-factor and extinction ratio defined as Q=20log10 [(μ1-μ0)/(σ1+σ0)] and ER=10log10 (μ1/μ0) are used to evaluate the operation performance, where μ1 and μ0 are the average power of logical ‘1’ and ‘0’ of the eye diagrams at the sampling time, while σ1 and σ0 are the corresponding standard deviations. Note that the performance degradation of Sum/Difference and Borrows shown in Fig. 4(c), Fig. 4(f), and Fig. 4(g) can be explained with the fact that signals A and B are not depleted completely when their data bits are both ‘1’. Such phenomenon can be also clearly seen from Fig. 3(c), Fig. 3(f), and Fig. 3(g). As shown in Fig. 4(d), the Carry of sum-frequency wave (3.1 ps) is compressed compared with the input signal (5 ps). However, due to walk-off effects  caused by GVM between the sumfrequency wave in the 0.77-μm band and signal, pump, idler waves in the 1.55-μm band, the Carry of idler (6.4 ps) shown in Fig. 4(e) is broadened.
Figure 5(a) shows the dependence of the idler pulse width on the length of the PPLN waveguide (L). It can be seen that the idler pulse is compressed when L<22 mm or L>38 mm and broadened as 22 mm<L<38 mm. Fig. 5(b) and Fig. 5(c) depict the changes of Q-factor (Sum/Difference, Borrows, OR logic gate) and ER (Sum/Difference, Borrows) against the length of the PPLN waveguide. It is to be noted that the optimized waveguide length is approximately 36 mm, approaching the maximum Q-factor and ER. This behavior can be briefly explained as follows. As shown in Fig. 3(c), Fig. 3(f), and Fig. 3(g), whether two signals with both data bits of ‘1’ are completely depleted in the SFG+DFG processes directly influences the performance of Sum/Difference and Borrows. According to the previous analyses , the longer the PPLN waveguide, the more deeply two signals are consumed and the better the performance achieved. However, the walk-off effects  between the sum-frequency wave in the 0.77-μm band and signal, pump, idler waves in the 1.55-μm band also affect the operation performance, which requires a shorter waveguide to be utilized. As a result, there is a trade-off on choosing the length of the PPLN waveguide, thus an optimal waveguide length can be found reaching the largest Q-factor and ER.
Figure 6 further illustrates the tunable performance. When the wavelengths of signals A and B are kept at 1550.0 and 1538.0 nm, respectively, both pump and idler wavelengths can be tuned in a wide wavelength range larger than 110 nm with 3-dB Q-factor penalty in Fig. 6(a) and 130 nm with 2.1-dB ER penalty in Fig. 6(b). Meanwhile, by setting the pump wavelength at 1555.0 nm and fixing the sum-frequency wavelength at 772.0 nm, generating the idler wavelength at about 1533.2 nm, the wavelengths of signals A and B can be also changed in a wide wavelength range larger than 43 nm with 3-dB Q-factor penalty in Fig. 6(c) and 56 nm with 3-dB ER penalty in Fig. 6(d). Therefore, Fig. 6 exhibits that flexible operation with great tunability can be conveniently achieved with the proposed scheme.
Remarkably, in the above calculations, the step lengths for time (t) and distance (z) are taken as about 0.2 ps and 50 μm, respectively. In order to verify the calculation accuracy, the evolvement of the total energy of all interacting optical waves along the PPLN waveguide are compared with that of the input signals and pump wave. It is found that the difference of the total energy propagating along the PPLN waveguide is small, not exceeding 0.8%, which verifies that the law of the energy conservation is satisfied with the acceptable accuracy for the simulations. The calculation accuracy can be further improved by appropriately reducing the time and distance step lengths. Note that, the calculations can be also performed by using other methods such as split-step Fourier transform . For different simulation methods, by properly choosing the step lengths for the simulations, the same order of the accuracy of calculations can be obtained, achieving similar results of the parameters of eye diagrams, pulse width, Q-factor, ER, and tunability.
We have proposed and numerically demonstrated, for what we believe is the first time, all-optical simultaneous half-adder, half-subtracter, and OR logic gate at 40 Gbit/s on the basis of SFG+DFG using only one PPLN waveguide. The eye diagrams, pulse width, Q-factor, ER, and tunability are simulated, exhibiting attractive operation performance with great flexibility.
With further improvement, the performance is possible to be improved by optimizing optical powers. Additionally, various other all-optical logical gates such as NAND, XOR, NXOR,and NOR based on PPLN waveguide are under way to be investigated, which may become potential candidates for future high-speed all-optical signal processing applications.
This work was supported by the National Natural Science Foundation of China under Grant No. 60577006, and by the program for New Century Excellent Talents in University (NCET- 04-0694).
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