Traditionally, Single Photon Avalanche Diodes (SPADs) are fabricated using dedicated processes that require additional technological steps when compared to standard CMOS. Instead, this paper presents the design of SPADs that attain good performances, by using a standard high-voltage CMOS process. The detector is monolithically integrated together with an Active Quenching Circuit (iAQC), a counter, and a serial communication interface. This opens the way to the design and fabrication of ultra compact multi-channel single-photon counters.
©2007 Optical Society of America
This paper deals with the design and characterization of the first ever reported monolithic Single-Photon Counter chip. Traditionally, the specific technological requirements of state-of-the-art Single Photon Avalanche Diodes (SPADs) did not allowed their fabrication through a standard CMOS technology, because it could not guarantee satisfactory performances, in particular concerning noise (dark-counting rate and after-pulsing effect). This fact limited the possibility of size reduction for a Single-Photon counting system, since different microelectronic chips have to be assembled together.
However, in recent years, the availability of High-Voltage CMOS processes with ever increasing degree of purity opened the way to the development of SPADs fabricated in a completely standard CMOS technology [1–2], though performances resulted to be acceptable only for detectors with a very small diameter and only a passive quenching was implemented. Moreover, CMOS SPADs have also the significant plus of being monolithically integrable with ancillary electronics, in order to build single-chip single-photon counters. The availability of such counters would simplify the design of multi-channel single-photon systems, like those required for Adaptive Optics or Micro-Array-based biological analysis .
We developed a complete chip, comprising the SPAD detector, the integrated active quenching circuitry (iAQC), counting and communication electronics. This is a major improvement over previously published works, in which only a part of the photon counting setup was integrated, usually with poor detector’s performance and diameter . The first part of the paper describes the chip in detail, whereas the second part illustrates the experimental characterizations. In particular, it is shown how the use of an integrated iAQC helps in mitigating afterpulsing effect, which in previous attempts resulted to be the limiting factor for on-field use of CMOS SPADs, due to the use of a simple passive quenching approach.
2. Chip architecture
The architecture of the CMOS Single Photon Counter chip is shown in Fig. 1, whereas a microphotograph of the chip is shown in Fig. 2. The CMOS SPAD has a 12 μm-diameter and is connected to an iAQC, similar to that described in Ref. , but featuring also a digital hold-off time control stage, in order to allow a remotely programmable control of the dead time.
The iAQC provides a TTL output, that is both routed outside the chip and fed to the Counting Stage. The external TTL output is useful when the user is interested in exploiting the timing capability of the SPAD, using the Time-Correlated Single-Photon Counting technique . Also the Gate is controlled both with a dedicated pin and through the serial interface, thus allowing both hardware and software enable controls.
The Counting and Communication Stage (CCS) collects the pulses from the iAQC in user-programmable time-slots and manages the communication with a remote PC. The CCS is composed by:
- 1) a synchronous counter with 20 bit resolution;
- 2) a programmable window generator, that generates the measurement time-slots, starting from an external clock signal;
- 3) a digital hold-off control stage that allows a remote adjustment of the hold-off time, from 5 ns up to 1265 ns in 5 ns-steps;
- 4) a serial interface compliant with the RS-232 protocol, able to communicate at bit-rates ranging from 9,600 bps to 3 Mbps, according to the external clock in use.
The chip requires only an external clock signal (in the range of few MHz) and a level shifter (e.g. MAX232) to be fully operative. If bit-rates higher than 115 kbps are required, the level shifter can be replaced with a USB-serial converter, such as the FT232BM.
3. CMOS SPAD
SPADs are usually fabricated in custom technologies to achieve low thermal generation, and to withstand the high-voltage level (tens of Volts) applied to the detector and the high-current flow (tens of mA) reached at each ignition of the avalanche multiplication process. In this work, we conceived the fully CMOS compatible structure shown in Fig. 3. The device was fabricated using the same High-Voltage 0.8 μm double-poly, double-metal CMOS process from AustriaMicroSystems, already used for the development of the iAQC .
In a CMOS process, the substrate is usually p-doped and it is the common bulk of all NMOSFETs. Instead PMOSFETs are built inside n-doped wells. In order to avoid any unwanted direct biasing of parasitic diodes between source/drain regions of NMOSFETs and substrate, this latter is commonly kept to a ground voltage. In custom SPAD structures, such as the one reported in Ref , the epilayer p is usually used as the anode of the SPAD, and isolation between detectors is obtained using a deep n-doped diffusion that reaches the n-substrate. This process step is not present in standard CMOS technologies. For this reason, in order to guarantee the electrical isolation of the detector with respect to the surrounding electronics, the SPAD structure was modified as shown in Fig. 3.
A shallow p+ implantation (used for low-voltage PMOSFETs source/drain regions) forms the active p+n junction at the top of a 7 μm-deep n-well, employed as the bulk of high-voltage PMOSFETs in the original process. A deeper n-doped enrichment (obtained by high-voltage NMOSFETs source/drain regions) defines the high-field region of the detector, with a breakdown voltage Vbd = 16 V, thus avoiding edge-breakdown. Since we could not be sure of the effectiveness of the enrichment, a guard-ring built using the deep p-doped diffusion of high-voltage PMOSFETs drain/source regions was also employed.
During operation with the iAQC, the SPAD cathode is tied to a positive supply through the sense resistor of the iAQC, while its anode is held to a constant negative supply. The breakdown voltage between the deep n-well cathode and the wafer p-substrate held at ground is above 55 V, and this guarantees a correct behaviour of the device.
4. Integrated AQC
The iAQC integrated in the Single-Photon Counter is almost identical to the one already described in Ref. . However, in order to fully exploit the communication capability of the chip, we added the feature to select between a standard analog hold-off time regulation and a novel digital adjustment. The iAQC is based on a mixed passive-active quenching stage, shown in Fig. 4, able to quiescently bias the detector to +Vhigh (slightly higher than the desired overvoltage, i.e. excess above breakdown) through a resistive ballast, and to keep the voltage at node (A) below, but close to, the voltage threshold of Squench transistor. The onset of the avalanche current starts a passive-quenching action, that increases the voltage drop across RB and quickly turns Squench on, thanks to a patented regenerating feedback loop . The active-quenching action is thus started, quickly pulling the detector’s cathode down to ground. Since -Vlow is slightly lower than Vbd, the SPAD is eventually turned off. The control logic senses the detector’s ignition and produces a standard TTL output pulse. Then the logic holds the detector off for an user-programmable hold-off time, in order to reduce the probability that a subsequent correlated ignition (afterpulse) is triggered by a trapped carrier release. Eventually the detector is reset to its quiescent condition above breakdown, through Sreset.
5. Counting and communication stage
The Counting and Communication Stage (CCS) is built around a Finite State Machine, whose current state is a function of commands received from the remote computer. These commands enable several functions:
- a) set the control lines of the iAQC (Gate and hold-off time control);
- b) set the duration of the integration windows;
- c) start and stop the transmission of accumulated counts to the remote computer;
- d) transmit diagnostic information to the remote computer.
The following paragraphs will provide a brief description of the communication protocol and outline the CCS architecture.
5.1 Communication protocol
The communication between the CCS and the remote PC takes place through two serial lines, RX and TX, according to RS-232 specification. Data transmission is done in sequences of 10 bit with fixed duration, but with no limit on the time delay between two consecutive sequences. The symbol frequency depends on the frequency of the external clock and can be as high as 3 Mbaud with a 24 MHz clock.
The CCS includes a Finite State Machine that changes its stage according to the bytes received from the computer. The transmission of a command is done by sending to the CCS a sequence of 3 or 4 bytes composed by a Start byte, the peripheral ID (identifier), the command code and an optional parameter.
The Finite State Machine behaves as follows. If the byte START is received, the machine moves to the VERIFY state, waiting for the correct Peripheral ID. If the following byte is PER_ID, the machine moves to the READY state, waiting for a command. If the next byte is a valid command that requires a parameter, the machine moves to the x_PARAM state, waiting for the last byte, otherwise returns to the IDLE state. If the command required a parameter, the IDLE state is reached after the reception of the parameter. If the machine receives the START byte, it always moves to the VERIFY state.
5.2 Data transmission
When the data transmission is enabled with the GO_CM command, the CCS starts to accumulate the counts occurred during each integration window, saving the result in a 20 bit register at the end of each window. During the time elapsed between two subsequent register’s update, its content is sent through the serial communication line. For short integration windows, the available time is not enough to transmit all 20 bit, for this reason the number of byte transmitted is adjusted according to the duration of the integration window in use, since the maximum number of pulses coming from the iAQC during an integration window is limited by the maximum operative frequency of the iAQC (about 30 Mcps, counts per second). For instance, for an integration window of 5 μs, which requires a minimum date rate of 2 Mbaud, the maximum number of pulses from the iAQC is 150, which can be transmitted with a single byte.
The Counting and Communication Stage is composed by several functional blocks, as visible in Fig. 5. It was built using the digital standard cells available in the technology. This choice not only simplified the design of the schematic, by using the Verilog language, but permitted also to self-generate the layout, with a considerable saving of design time and silicon area.
The CCS is controlled by an internal Clock signal that provides synchronization among stages. The clock is fed to all blocks by a Clock Buffer with high driving capability. The internal clock frequency is equal to the external one in High Speed Mode, and equal to the external clock frequency divided by 8 in the Low Speed Mode.
The serial data coming from the remote computer through the RX line are received by the Asynchronous Receiver that recovers the useful bits, organizes them in parallel form and synchronizes the incoming data with the internal clock. Data are then processed by the Controller block, that implements the Finite State Machine described in the previous paragraphs. According to the received command, the Controller drives the control lines of all other blocks. The Timer generates a square wave signal, with a period equal to the desired duration of the counting window, during which the Synchronous Counter accumulates the pulses from the iAQC. At the end of each window, the Register latches the data from the Counter in order to permit their transmission, which is eventually performed by the Asynchronous Transmitter through the TX line. The synchronization between pulses from the iAQC and time intervals generated by the Timer is carried out by an Arbiter block, which avoids faulty behaviours due to the simultaneous switching of reset and Counter’s increment.
6. Experimental results
We performed a complete characterization of the Single-Photon Counter, including both functional tests on the electronics and measurements of the SPAD’s characteristics. The full chip, when operated at 5V-overvoltage at the maximum counting rate of 30 Mcps and at the maximum communication frequency of 3 Mbps, draws 10 mA from the +5V supply, 15 mA from the +Vhigh=10V supply and 2.5 mA from the -Vlow= -11V supply.
Figure 6 shows the cathode waveform during an avalanche and the current that flows in the SPAD when biased at 5 V-overvoltage. The peak current reaches 8 mA and then quickly drops thanks to the passive quenching due to the RB resistor. After about 7 ns, the iAQC starts its active quenching, thus the current vanishes to zero, leading to an overall duration of the avalanche process of about 8 ns. After a 50ns hold-off time, the iAQC core resets the detector to its quiescent biasing. It is possible to see that the combined use of a passive semi-quenching, followed by an active one, swiftly quenches the current in about 8 ns, thus reducing charge trapping. In Fig. 6 it is also possible to see an afterpulsing event that occurs during the previous reset phase and for this reason the current pulse in the detector has an extended duration: the reset duration is automatically adjusted by the electronics, in order to be sure that the SPAD is properly reset to Vhigh (see Fig. 4) and thus ensuring the exploitation of the minimum required reset time at each operating conditions. When the hold-off duration is adjusted to its minimum, the chip can then be ignited by another photon after just 34 ns from the previous ignition, thus allowing a maximum saturated counting rate of 30 Mphoton/s, as visible in Fig. 7. The module also provides gated-detector operation, controllable both by hardware (through an external GATE input) and software (by sending a command byte via the serial interface), that can be exploited when signal photons occur only during short and well-defined intervals, like in laser-induced fluorescence excitations . In Fig. 8 it is possible to see an example of gated-mode operation, with the hold-off set to its minimum and the gate-on time, during which the circuit can detect an incoming photon, is set to 50ns. A photon is detected in the first and third gate periods, whereas no photon is detected in the second one.
The correct behaviour of the Counting and Communication Stage has been verified at different bit-rates, ranging from 9,600 bps to 3 Mbps, using an external USB-serial converter for bit-rates higher than 115,200 bps. The electronics correctly handled all commands and returned the counting acquired during measurement windows of the desired duration. The values transmitted were verified using an external counter connected to the TTL output of the iAQC. In Fig. 9 it is possible to see an example of communication at 3Mbps, with time-windows duration set at 6.5μs.
Finally, a full characterization of the SPAD was made, as reported in the following paragraphs. All measurements refer to a typical 12 μm diameter SPAD, and were made using the complete chip as a whole, quenching the detector, counting the ignitions and communicating with a remote PC using the embedded iAQC and CCS. Only when time interval measurements were required, an external timing setup was used.
6.1 Dark counting rate
The Dark Counting Rate for the detector has been measured at different overvoltages and temperatures. Results are shown in Fig. 10. As it can be noted, decreasing the temperature is quite effective down to 0 °C, but the decrease is not so evident at lower temperatures. Moreover the increase with overvoltage is almost exponential. These two facts indicate that dark counts are dominated by tunneling , due also to the low SPAD breakdown voltage.
Concerning the level of dark-counts, it should be pointed out that, even if these SPADs have a 12 μm diameter, at room temperature they are comparable to 50 μm diameter detectors built in custom processes . In addition, the decrease of dark-counts with temperature is less evident. This indicates that custom technology should still be preferred if large diameter and low dark-counts are required. However, it is worth noting that for short integration time-windows the major limit to achieve a sufficient SNR is represented by the shot noise of the incoming photon flux and not by the detector’s dark counts . For instance, with an integration time of 1 ms, the minimum signal to achieve an SNR of 3, even with no detector noise, is 9000cps. This value makes negligible the contribute to noise of the 500 cps of the detector at 5V-overvoltage and room temperature.
6.2 Photon detection efficiency
The Photon Detection Efficiency shown in Fig. 11 has been measured over the visible range at different overvoltages, by means of a monochromator and an integrating sphere. The peak is of approximately 45% around 500 nm, the efficiency remains above 20% over all the visible range, and it is still a few percent in the near-infrared up to 950 nm. These results are remarkably better than those of S1 photocathodes and of other SPAD devices fabricated in CMOS processes [1–2–4].
However, it can be noted that PDE is lower than that of custom SPAD at the same overvoltage . This is due to a thinner depletion region, and thus to a lower photon absorption. The ringing on the efficiency curves is on the other hand caused by the thick interlevel stack of Silicon Dioxide and Nitride that was not removed from the active area and that acts as a resonance layer. Unfortunately, we could not further investigate this issue, since these technological details are kept confidential by the manufacturer. Figure 12 shows that PDE almost saturates at 10 V-overvoltage, indicating that avalanche triggering probability is almost unitary in this condition. The different shape in the 450nm and 500nm curves indicates that the dependence of triggering probability on the overvoltage is not the same for all the wavelengths. This is probably due to the different absorption depths for the different wavelengths, and thus to the effective field experienced by each photogenerated couple. Since exact doping profiles are confidential, we could not verify this possibility.
6.3 Afterpulsing probability
In measurements employing SPAD detectors, noise is caused by Poissonian fluctuations of detector counting-rate. This effect is always present, even if the detector has no photonic signal, and its intensity (i.e. the root mean squared of the fluctuations) is proportional to the mean number of pulses per second, i.e. the dark-counting rate. Moreover, during each avalanche current pulse, some avalanche carriers are trapped by deep levels; then they are subsequently released after a time that spans from few nanoseconds (for the best silicon SPADs) to several milliseconds (for typical InGaAs/InP SPADs), thus generating other correlated avalanche injections.
The effect is regenerative and is known as “afterpulsing” and drastically degrades detector performances. Hence, in designing SPAD process flows (fabrication recipes), gettering processes are required to minimize not only generation centres (electronic level close to the middle of the band-gap), but also trap levels (deeper electronic level, closer to the edges of conduction or valence bands).
Since we used a standard CMOS processing, with no control on the proper gettering steps to reduce afterpulsing, we decided to perform a complete characterization of charge trapping in the SPAD fabricated in this technology. The sub-microsecond lifetime of trap levels prevents the use of standard characterization techniques, based on measurements of capacitance or current transients. In order to accurately investigate the effects of carriers trapping during an avalanche and the subsequent afterpulsing phenomena, the experimental technique “Time-Correlated Carrier Counting” (TCCC)  was introduced, similar to the “Time-Correlated Photon Counting” (TCPC) , which is largely used in studies of fluorescent decays. This method allows to measure the carrier release probability from trapping centres located in the space-charge region, involved during SPAD operation; it gives both the typical release time constants of the traps and an estimate of their concentration.
The TCCC approach was developed for studying trap decays, by exploiting the sensitivity to single carriers and picoseconds resolution of the detector itself. Fig. 13 shows the principle of the method, which essentially consists in:
- 1) filling the deep levels (traps) with a pulsed stimulus;
- 2) measuring the time interval from the filling pulse to the detection of the first released carrier;
- 3) repeating the procedure for collecting a histogram of carriers emissions as a function of time.
Deep levels can be populated by means of current or light pulses. In our case, we adopted the avalanche current pulses (i.e. the dark-counting pulses) generated by the detector itself. Using the avalanche current pulses has the advantage of filling only those traps involved in normal device operation. A pulsed laser could be employed for triggering the SPAD avalanche current, as done in Ref , thus reducing the total measurement time, but the devised experimental setup is simpler and more compact.
The experimental setup is shown in Fig. 14. The SPAD is biased above breakdown and is kept in dark. The iAQC output pulses are sent into two coaxial cables by means of a balanced impedance (50 Ω) splitter. The signal from one cable is delayed and used as the “Start” signal for the Time-to-Amplitude Converter (TAC). The other (not delayed) provides the “Stop” signal. The TAC converts the delay between Start and Stop in a voltage signal which is digitised by an ADC, and then stored and classified by a Multi-Channel Analyser (MCA).
Figure 15 shows the temporal sequence of signals used to measure the delay between a filling avalanche (first pulse) and the subsequent detrapping avalanche (second pulse). The splitter and the delayer act as a multiplexer, which sends the (first) filling pulse to the Start input of the TAC, and the (second) after-pulse to the Stop input. It is worth noting that the delay introduced to generate the replica (the Start signal) must not be longer than the iAQC dead-time, otherwise afterpulses occurring during the time interval from the end of the first pulse dead-time to the arrival of the Start would not be measured: their Stop signal would reach the TAC before the Start, hence they would not be detected. The measurement is repeated for a large number of avalanche pulses, this obtaining an histogram with a sufficient Signal-to-Noise-Ratio, i.e. high enough to make the afterpulsing component clearly recognisable and quantifiable despite intrinsic measurement fluctuations. It represents the probability (y-axis) to have an afterpulse after a specific time elapsed (x-axis) from the primary avalanche. If the aforementioned condition on the introduced fixed delay is fulfilled, such arbitrary chosen delay has no effect on the histogram and on the measurement itself.
Figure 16 shows the measurements of the afterpulsing probability for a fabricated CMOS SPAD, for two different values of the hold-off time and at a 5 V-overvoltage. The release time constant is 3.5 ns in both cases; the total afterpulsing probability falls from 2.6% down to 0.02% when the hold-off time is increased from 55 ns to 200 ns. These levels are definitely lower than other previously reported for CMOS SPAD , and make it possible to employ the Single-Photon Counter chip up to very high counting rates of several Mcps. Comparison with the afterpulsing level of custom technology SPAD  is less favourable if referred to the same hold-off time and overvoltage, however the relatively short trap release time of only few tens of nanoseconds allows to obtain comparable or even better value with a modest increase of the hold-off time and maintaining the same overvoltage.
The beneficial effect of the hold-off time on the afterpulsing probability is well known , and it is one of the main reasons that encouraged the use of AQCs, together with the reduction of the total charge flowing in the SPAD during an avalanche. However, the use of an iAQC can also be exploited in another manner. The iAQC allows the user to set not only the voltage above breakdown during the quiescence phase (overvoltage, Vex), but also the voltage below breakdown during the hold-off phase (undervoltage). Actually, in order to change the desired undervoltage while keeping the same overvoltage, both +Vhigh and -Vlow must be modified, and this requires the use of a flexible quenching circuit. The overall voltage applied to the SPAD is given by +Vhigh+∣-Vlow∣. Since the iAQC brings the cathode to ground during the hold-off time, the undervoltage is given by +Vhigh-Vex. It is thus possible to independently fix both the overvoltage and the undervoltage. Simpler quenching designs  do not allow any adjustment of the upper supply voltage, usually fixed at +5V, and this implies that −Vlow fixes both the overvoltage and the undervoltage at the same time.
It is well known  that detrapping is more efficient at high fields, and thus a low undervoltage could help in reducing the afterpulsing probability. This is indeed true for the devised CMOS SPAD, as shown in Fig. 17. By lowering the undervoltage from 7 V down to 3 V while keeping the same 5 V-overvoltage, it is possible to attain the same afterpulsing probability, even reducing the hold-off time from 200 ns to 55 ns. Unfortunately, we could not perform any device simulations in order to quantify the electric field inside the detector at the different applied undervoltages, since the exact technology doping profiles are confidential.
6.4 Timing resolution
In photon timing applications, it is important to measure the photon arrival time with very high precision and low time jitter. The timing resolution of the chip was checked in a conventional Time-Correlated Photon Counting set-up . Both the detector and the quenching circuit contribute to the total jitter of the system. Figure 18 shows the detector response to an 820 nm-pulsed laser at 10 V-overvoltage: the full-width at half maximum (FWHM) is 36 ps. This value is comparable to the best results obtained with discrete-component circuits and custom process SPAD . The exponentially decaying tail, with 910 ps-time constant, is due to photons absorbed in the SPAD neutral layer. The resolution obtained is thus adequate for the most demanding applications, such as obtaining millimetric resolution in time-of-flight measurements (e.g. in LIDAR) and optical time-domain reflectometry (OTDR). Finally, Fig. 19 shows the attainable FWHM at different overvoltages. Resolution does not exceed 50ps even down to 3V-excess bias.
In this work we developed the first ever-reported monolithic single photon counter in a standard high-voltage CMOS technology. The obtained detection performances, especially detection efficiency and timing resolution, are comparable with those of detectors built in custom processes. The full integration of single-photon detector plus electronics provides a fast quenching of the avalanche current, and the user-selectable hold-off time reduces afterpulsing effect, that is usually the limiting factor of CMOS SPADs. Thanks to the active-reset, the chip ensures repeatable and reliable operating conditions, thus leading to reliable detection efficiency and noise levels even at high counting rates. The chip is fully configurable, thus opening the way to the development of high-performance very compact, multi-channel single-photon systems for biological and genetic analytical assays, like quad-cells for centring and tracking a spot or four-bases detection sites for DNA analysis, etc. Such applications usually require a small number (up to few tens) of photon counters on well known spot positions, hence the low fill-factor of the proposed chip is not a limiting issue as for imaging photodetector arrays.
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