## Abstract

Using a simplified chirp *z*-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp *z*-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

© 2014 Optical Society of America

## 1. Introduction

This work is an extension of the author’s recent article [1]. By direct realization of the CZT algorithm (which is referred to as the non-simplified CZT algorithm), a novel reconfigurable OCZT processor synthesized using the silica-based PLC technology has been presented, to the author’s knowledge, for the first time in [1]. As the first important application of the designed tunable OCZT processor in [1], [2] has presented the design of a tunable ODFT processor (which is a special case of the tunable OCZT processor in [1]) and its application as a tunable optical demultiplexer at the receiver of an optical fiber OFDM transmission system. Several case studies of the author’s novel tunable ODFT-based OFDM demultiplexer have been investigated to demonstrate several of its unique capabilities over the existing non-tunable ODFT-based OFDM demultiplexers [2]. However, in [1], the architecture of the tunable OCZT processor was rather complex because the design was based on the non-simplified CZT algorithm (in which no simplifications were made on the algorithm) that involved a very large number of $N\times L$ multiplications and additions. As appeared in Eq. (2), *N* is the number of input discrete-time samples $x[n]$ to be transformed into *L* number of output frequency samples $X[k]$ due to the CZT operation. As such, the number of optical components in the synthesized adaptable OCZT processor was very large (especially when *N* and *L* were large) and that there were a number of waveguide crossings or intersections which would make fabrication difficult [1].

To overcome these drawbacks in [1], this paper presents a more simplified CZT algorithm based on the discrete-time convolution method to come up with a much simpler architecture of the tunable OCZT processor design. The simplified CZT algorithm only requires $~\left(N+L\right){\mathrm{log}}_{2}\left(N+L\right)$ multiplications and additions which are much smaller than those of the non-simplified CZT algorithm in [1], as described above. Hence, it is shown that the number of optical components in the simpler architecture of the tunable OCZT processor in this work is much less than those in [1]. Furthermore, unlike in [1], the adaptable OCZT processor with a simpler architecture in this work has no waveguide crossings or intersections and this will make fabrication much easier. Section 2 presents the simplified CZT algorithm using the discrete-time convolution technique. Using the simplified CZT algorithm, section 3 describes the synthesis of the reconfigurable OCZT processor with a simpler architecture using the silica-based PLC technology. Section 4 presents the design of an ODFT as a special case of the synthesized OCZT and its potential application. Conclusion is given in Section 5.

## 2. Simplified CZT algorithm

This section presents a simplified CZT algorithm based on the discrete-time convolution technique [3–6]. An input analog complex-valued signal $x(t)$ is sampled at the sampling period *T* (or unit-time delay of a filter) to yield a discrete-time *N*-point sequence $x[n]$ so that $x[n]=x(nT)={x(t)|}_{t=nT;n=0,1,\dots ,N-1}$ (see Fig. 4(a) of [1]). The unilateral *N*-point *z*-transform of $x[n]$ is given by [3–6]

*z*-transform parameter is defined as $z=\mathrm{exp}(j\omega T)$, where $j=\sqrt{-1}$ and $\omega $ is the angular frequency. It is assumed that the sum in Eq. (1) converges for all

*z*except at

*z*= 0. In Eq. (1), $x[n]$ is transformed into its complex-plane representation $X(z)$ which is the spectrum of $x[n]$. By computing Eq. (1) at a set of

*L*equally-spaced frequency samples on an arbitrary contour in the

*z*plane, i.e.,$z=\left\{{z}_{k}\right\}\text{=}\left\{{z}_{0}{z}_{1}\dots {z}_{L-1}\right\},$ the

*L*output frequency samples $\left\{X[k]\right\}\text{=}\left\{X[0]X[1]\dots X[L-1]\right\}$ are given by [3–6]where

*N*and

*L*are arbitrary integers and

*k*by

*n*and

*n*by

*k*in Eq. (7) to giveLet Putting Eq. (10b) into Eq. (9) giveswhere where * denotes the convolution operation. Equations (12a) and (12b) mean that the output discrete-time sequence $y[n]$ is given by the discrete-time convolution of an input discrete-time sequence $g[n]$ with the discrete-time impulse response $h[n]$ of a linear time-invariant system which is here a finite-impulse response (FIR) filter. Then $y[n]$ is multiplied by the sequence ${V}^{-{n}^{2}/2}$ to give the CZT output $X[n]$ according to Eq. (11). In Eqs. (11) and (12a), the range of $g[k]$ is $k=0,1,\dots ,N-1$ and the ranges of both $X[n]$ and $y[n]$ are $n=0,1,\dots ,L-1.$ Using these results, it can be easily shown from Eq. (12a) that the range of $h[n]$ in Eq. (10a) is given by $-(N-1)\le n\le L-1$. HenceIn Eq. (13), $-(N-1)\le n\le L-1$ corresponds to the right number (i.e., no more and no less) of filter coefficients in the impulse response $h[n]$, avoiding the use of extra or redundant filter coefficients for structural simplicity. In Eq. (13), $h[n]\text{for}n<0$ corresponds to a non-casual filter which is not practical for real-time implementation. To make $h[n]$ a casual impulse response for real-time implementation$(\text{i}\text{.e}\text{.,}h[n]\text{for}n\ge 0),$ delay $h[n]$ by $(N-1)$ samples to become $h[n-(N-1)]$ and a new variable ${h}_{1}[n]$ is thus defined as ${h}_{1}[n]=h[n-(N-1)]=h[n-N+1]$. Substituting this expression into Eq. (13) givesNote that $-(N-1)\le n\le L-1$ in $h[n]$ in Eq. (13) has been changed to $\text{0}\le n\le L+N-2$ in ${h}_{1}[n]$ in Eq. (14) because $h[n]$ has been delayed by $(N-1)$ samples to give ${h}_{1}[n]$. Putting ${h}_{1}[n]=h[n-(N-1)]$ from Eq. (14) into Eqs. (12a) and (12b) gives Since $h[n]$ in Eq. (13) and hence Eq. (12) have been delayed by $(N-1)$ samples, $y[n]$ in Eq. (12) must also be delayed by the same $(N-1)$ samples because $g[k]$ $(k=0,1,\dots ,N-1)$ in Eq. (12) remains unchanged. Hence, in Eqs. (15a) and (15b), $n=0,1,\dots ,L+N-2$ for $y[n]$ because ${h}_{1}[n]$ in Eq. (14) also has $n=0,1,\dots ,L+N-2$. Since $y[n]$ has been delayed by $(N-1)$ samples according to Eq. (15), $X[n]$, the chirp factor ${V}^{-{n}^{2}/2}$ and $y[n]$ in Eq. (11) must also be delayed by the same $(N-1)$ samples such thatSince $X[n]$ in Eq. (16) has been delayed by $(N-1)$ samples, the

*L*useful (or correct) output frequency samples ${X}_{\text{u}}[n]$ correspond to the samples of $X[n]$ that are $(N-1)$ samples in advance such thatEquation (8) can be written aswhere Putting Eq. (5) into Eq. (14) giveswhere Putting Eq. (5) into Eq. (16) giveswhere Note that Eq. (20d) is the same as Eq. (17). Equation (20a) gives all (i.e., $L+N-1$) the output frequency samples. However, the

*L*useful output frequency samples are $\left\{{X}_{\text{u}}[0]{X}_{\text{u}}[1]\dots {X}_{\text{u}}[L-1]\right\}=\left\{X[N-1]X[N]\dots X[L+N-2]\right\}$ according to Eq. (20d) while $\left\{X[0]X[1]\dots X[N-2]\right\}$ in Eq. (20a) are the redundant or non-useful output frequency samples which should not be implemented to simplify the architecture. In summary, Eqs. (18a), (15a), (15b), (19a), (20a) and (20d) describe the simplified CZT algorithm using the discrete-time convolution method and its block diagram representation is shown in Fig. 1. The FIR filter with an up-chirp impulse response ${h}_{1}[n]$ defined in Eq. (19a) is called a

*chirp*filter for the following reason. The algorithm is called the simplified

*chirp z*-transform (CZT) algorithm because ${h}_{1}[n]$ is a complex exponential sequence with linearly increasing frequency. These kinds of signals (or impulse responses) are called

*chirp*signals (or impulse responses) in radar systems and hence the name

*chirp*in the simplified CZT algorithm [3–6]. Hence the FIR filter with ${h}_{1}[n]$ defined in Eq. (19a) is called the

*chirp*filter. Radar and sonar signal processing systems similar to the simplified CZT system shown in Fig. 1 have been widely used for pulse compression [3–6]. The simplified CZT algorithm basically consists of three operations in the following sequential order (see Fig. 1): (i) pre-multiply down chirp; (ii) convolution; and (iii) post-multiply down chirp. Down chirp means that there is a negative sign in $\alpha [n]$ [Eq. (18c)] and also in $\gamma [n]$ [Eq. (20c)] while up chirp means that there is a positive sign in $\beta [n]$ [Eq. (19c)].

## 3. Synthesis of a reconfigurable OCZT processor with a simplified architecture

Using the simplified CZT algorithm described in Section 2, this section presents the synthesis of a reconfigurable OCZT processor using the silica-based PLC technology [7–12]. Other integrated-optic technologies (e.g., the silicon-on-insulator (SOI) platform which is compatible with the complementary metal-oxide-semiconductor (CMOS) technology) could also be employed for the implementation of the reconfigurable OCZT processor [13,14]. Two designs of the tunable OCZT processor based on the same architecture are presented here to cater for different application requirements. The optical synthesis of $a[n]$ and $\alpha [n]$ is described as follows. As explained in the texts below Eq. (27b) and also in Eq. (33), the phase angle $\alpha [n]$ defined in Eqs. (18a) and (18c) can be realized using a thermo-optic-based tunable phase shifter (PS) [7–11]. While the amplitude $a[n]$ defined in Eqs. (18a) and (18b) can be realized using a thermo-optic-based tunable coupler (TC) with a coupling coefficient of between 0 and 1 (inclusive) [7–11, 15]. Applying $a[n]\le 1$ on Eq. (18b) gives

orNote here that $a[n]$ has been designed to be in the range of $0\le a[n]\le 1$ (rather than $a[n]>1$) so that it can be realized using a TC, eliminating the need to use an optical gain element which will be much more difficult to fabricate. Comparing Eq. (19b) with Eq. (20b) givesfrom which two possible designs are These designs have $a[n]\le 1$ and they are described in Sections 3.1 and 3.2, respectively.*3.1 Design 1: *$a[n]\le 1,b[n]\le 1,c[n]\ge 1$

In this Design 1, applying $b[n]\le 1$ on Eq. (19b) gives

Applying Eq. (24) on Eq. (21a) givesThis Design 1 requires $c[n]\ge 1$, and to avoid using an optical gain element to realize $c[n]\ge 1$, the following approach is employed. Also, $c[n]\ge 1$ cannot be implemented using a TC with a coupling coefficient of between 0 and 1 (inclusive) unless $X[n]$ in Eq. (20a) is normalized. Thus, normalize $X[n]$ in Eq. (20a) to giveUsing Eqs. (18a), (15a), (15b), (19a), (20a) and (20d) and Fig. 1, Fig. 2 shows the schematic diagram of the synthesized reconfigurable OCZT processor based on the silica-based PLC technology. Without loss of generality, the waveguide loss is neglected for ease of analysis. In Fig. 2(b), in assigning the notations $\left\{x[0]x[1]\dots x[N-1]\right\}$ at the inputs of the $g[n]$ block, the splitting loss of the $1\times N$ splitter in the serial-to-parallel converter is ignored for ease of analysis. Similarly, in Fig. 2(d), in assigning the notations $\left\{y[N-1]\dots y[L+N-3]y[L+N-2]\right\}$ at the inputs of the $X[n]$ block, the splitting loss of the $1\times L$ splitter in the serial-to-parallel converter is neglected for ease of analysis. However, these splitting losses will be taken into consideration below as shown in Eq. (27). The serial-to-parallel converters and the samplers shown in Figs. 2(b) and 2(d) are described below. The splitters and combiners in Figs. 2(b)-2(d), which consist of the cascade of Y-branch waveguides arranged in a binary fashion, can be designed using the wavefront matching method [12]. This type of splitter/combiner is better than a slab splitter/combiner, including a star coupler and a multi-mode interference (MMI) splitter/combiner, in terms of the uniformity of the splitter ratio [8]. To compensate for the splitting losses of the three splitters in Figs. 2(b)-2(d), the two *G* terms (the intensity gains) are provided by an EDFA at the input and another EDFA at each output:

*3.2 Design 2: *$a[n]\le 1,b[n]\ge 1,c[n]\le 1$

In this Design 2, just like Design 1 described in section 3.1, $a[n]\le 1$, and $a[n]$ and ${\alpha}^{\prime}[n]$ in Fig. 2(b) are described by Eqs. (32) and (33), respectively. In this Design 2, $b[n]\ge 1$ and applying this condition on Eq. (19b) gives

Applying Eq. (38) on Eq. (21a) givesSince $b[n]\ge 1$ in this Design 2 cannot be realized using a TC with a coupling coefficient of between 0 and 1 (inclusive), normalize ${h}_{1}[n]$ in Eq. (19a) to givewhere $n=0,1,\dots ,L+N-2$, $b{[n]}_{\mathrm{max}}$ $(b{[n]}_{\mathrm{max}}>1)$ is the maximum value of $b[n]$ and ${b}^{\prime}[n]=b[n]/b{[n]}_{\mathrm{max}}$ where $0\le {b}^{\prime}[n]\le 1$. Now $0\le {b}^{\prime}[n]\le 1$ can be implemented using a TC, and this is the same situation as $0\le {c}^{\prime}[n]\le 1$ in Design 1. In Fig. 2(c), the notation $b[n]$ for Design 1 must be changed to ${b}^{\prime}[n]=b[n]/b{[n]}_{\mathrm{max}}$ for Design 2 according to Eq. (40). Hence where $\left|{C}_{{b}^{\prime}[n]}\right|=\left|{C}_{n}\right|$ and $\angle {C}_{{b}^{\prime}[n]}=\angle {C}_{n}$. Also, in Fig. 2(d), the notation ${c}^{\prime}[n]$ for Design 1 must also be changed to $c[n]$ since $c[n]\le 1$ for Design 2. Thus where $\left|{C}_{c[n]}\right|=\left|{C}_{n}\right|$ and $\angle {C}_{c[n]}=\angle {C}_{n}$. Similarly, in Eq. (27b), replacing $c{[n]}_{\mathrm{max}}$ for Design 1 with $b{[n]}_{\mathrm{max}}$ for Design 2 givesIn Fig. 2(b), the *N* input discrete-time samples $\left\{x[0]x[1]\dots x[N-1]\right\}$ at the inputs of the $g[n]$ block can be generated using a serial-to-parallel converter and *N* gate-based optical samplers [7–10]. Together with the serial-to-parallel converter, the optical gates (or samplers) must synchronously sample the input continuous-time signal $x(t)$ over the time slot $T$and convert it into its discrete-time representation $\left\{x[0]x[1]\dots x[N-1]\right\}$ [Fig. 2(b)]. The optical gates can be implemented using electro-absorption modulators (EAMs) [7–10]. In Fig. 2(b), $x(t)$ is equally split (by a $1\times N$ splitter) into *N* signals which are relatively delayed (using delay lines in the delay array 1) by integer multiples of *T* and then time gated (by the optical samplers) so that the discrete-time samples $\left\{x[0]x[1]\dots x[N-1]\right\}$ will arrive at the respective input ports of the $g[n]$ block at the same time slot of *T* to achieve time synchronization according to Eq. (18a). In the delay array 1, the top waveguide has the largest delay of $(N-1)T$ to slow down $x[0]$ most because it is the fastest sample. Conversely, the bottom waveguide has the smallest delay to speed up $x[N-1]$ most because it is the slowest sample. As such, all the samples $\left\{x[0]x[1]\dots x[N-1]\right\}$ will simultaneously arrive at the inputs of the $g[n]$ block at the same time slot of *T*. In the delay array 2 of the $g[n]$ block, the delay lines differ by integer multiples of *T* so that the neighbouring samples of $g[n]=\left\{g[0]g[1]\dots g[N-1]\right\}$ at the output of the $N\times 1$ combiner are separated by *T*. $a[n]$ ${\alpha}^{\prime}[n]$in the $g[n]$ block implement Eqs. (32) and (33), respectively, and thus the $g[n]$ block is realized. However, to fabricate the whole device on the silica-based PLC platform, the optical gates shown in Fig. 2(b) are moved to the output ports of the tunable OCZT processor as shown in Fig. 2(d), without affecting the device characteristics due to its linearity property. The FIR filter shown in Fig. 2(c) is the implementation of Eqs. (15), (19), (34) and (35). In Fig. 2(d), the $X[n]$ block implements Eqs. (26), (36) and (37) and $X[n+N-1]$ relates to ${X}_{\text{u}}[n]$ according to Eq. (20d). Similar to the function of the serial-to-parallel converter in Fig. 2(b), the $L$ input discrete-time samples $y[n]=\left\{y[N-1]\dots y[L+N-3]y[L+N-2]\right\}$ (which are some of the FIR filter’s total $L+N-1$ output time samples in Fig. 2(c)) at the input of the serial-to-parallel converter in Fig. 2(d) are equally split (by a $1\times L$ splitter) into $L$ discrete-time samples which are relatively delayed (using the delay lines in the delay array 1) by integer multiples of *T* so that $\left\{y[N-1]\dots y[L+N-3]y[L+N-2]\right\}$ will arrive at the respective input ports of the $X[n]$ block at the same time slot of *T* to achieve time synchronization according to Eqs. (26) and (20d). In the delay array 1, the top waveguide has a larger delay of $(L-1)T$ to slow down $y[N-1]$ more because it is a faster sample. Conversely, the bottom waveguide has the smallest delay to speed up $y[L+N-2]$ most because it is the slowest sample. As such, all the samples $\left\{y[N-1]\dots y[L+N-3]y[L+N-2]\right\}$ will simultaneously arrive at the respective input ports of the $X[n]$ block at the same time slot of *T*. In the delay array 2 of the $X[n]$ block, the delay lines differ by integer multiples of *T* so that $X[n]$ defined in Eqs. (26) and (20d) can be realized. At the outputs, the *L* useful output frequency samples are ${X}_{\text{u}}[n]=X[n+N-1]\text{(}n=0,1,\dots ,L-1)$ according to Eq. (20d). To obtain time synchronization so that all the input time samples $\left\{x[0]x[1]\dots x[N-1]\right\}$ in Fig. 2(b) propagate in synchronism from one stage to the next, the waveguides (on which the TCs and PSs are placed) and the Y-branch waveguides inside the splitters and combiners must have the same delay. As such, the *L* useful output frequency samples $\left\{{X}_{\text{u}}[0]{X}_{\text{u}}[1]\dots {X}_{\text{u}}[L-1]\right\}$ will simultaneously appear at the respective output ports (i.e., before the gates and the EDFAs) of the tunable OCZT processor at the same time. Furthermore, on each waveguide path, the TC’s coupling coefficient $\left|C(k)\right|=\sqrt{0.5-0.5\mathrm{cos}\left(\phi (k)\right)}$ can also be adjusted to compensate for any non-uniform splitting ratio of the splitters and also for any non-uniform combining ratio of the combiners. On each waveguide path, the PS’s phase shift value can also be adjusted to be slightly more or less (if needed) than the designed value to compensate for any length deviation due to fabrication error of the waveguide path. A waveguide can be fabricated to the precision of 1 μm using the silica-based PLC technology [11].

From Table 1, it is clear that the proposed tunable OCZT architecture is much simpler than that reported in [1]. The choice of the *L* and *N* values depends on the application requirements [1,2].

One important application example of the proposed tunable OCZT processor based on the simplified CZT algorithm is described as follows. As explained in [1] (see Fig. 2(b) of [1]) and [2] (see sections 2 and 3 and Table 1 of [2]), by putting ${r}_{0}={R}_{0}=1$ into Eq. (3) (it is also Eq. (3) in [1,2]), a new tunable ODFT processor can be designed as a special case of the tunable OCZT processor based on the non-simplified CZT algorithm. The ODFT processor is tunable because ${\theta}_{0}$ and ${\varphi}_{0}$ in Eq. (3) can be continuously tuned to be within $0\le {\theta}_{0}\le 2\pi $ and $0<{\varphi}_{0}<2\pi $, respectively. While the current non-tunable ODFT processors designed using the fast Fourier transform (FFT) algorithm [7–10] also have ${r}_{0}={R}_{0}=1$ but ${\theta}_{0}$ and ${\varphi}_{0}$ cannot be tuned and must take the fixed values of ${\theta}_{0}=0$ and ${\varphi}_{0}=2\pi /N$ with $N=L$ (see Fig. 2(a) of [1]). As such, the current non-tunable ODFT processors (such as those described in [7–10]) are a special case of the tunable ODFT processor of [1,2]. Table 1 of [2] provides a summary of the unique advantages of the tunable ODFT processor based on the non-simplified CZT algorithm over the current non-tunable ODFT processors designed using the FFT algorithm. These unique advantages over the current non-tunable ODFT processors are also enjoyed by the proposed tunable ODFT/OCZT processor based on the simplified CZT algorithm in this work. The only difference is that the proposed tunable OCZT processor based on the simplified CZT algorithm here has a simpler architecture than that of the tunable OCZT processor based on the non-simplified CZT algorithm in [1,2].

## 4. A design example and its potential application

This section presents the design of a new type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT presented in Section 3 to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system [7–10]. Putting ${r}_{0}={R}_{0}=1$ (as required by an ODFT) into Eqs. (4)-(5) gives

*k*th output frequency sample ${X}_{k}(\omega )$; $k=0,1,\dots ,L-1$) is given by

*N*and

*L*are arbitrary integers, ${\theta}_{0}$ can be chosen to be within $0\le {\theta}_{0}\le 2\pi $, and ${\varphi}_{0}$ can be chosen to be within $0\le {\varphi}_{0}\le 2\pi $ provided that ${\varphi}_{0}\ge 2\pi /N$ to avoid overlapping of the neighbouring channels in the magnitude response. The chosen values of ${\theta}_{0}$ and ${\varphi}_{0}$ must satisfy the fact that the

*L*channels must lie within one normalized free spectral range (FSR) of 2π. Hence, the conventional ODFTs [7–10] are a special case of the new ODFT. As a design example, the new ODFT has ${r}_{0}={R}_{0}=1$, $N=8$, $L=7$, ${\theta}_{0}={50}^{\circ}$, and ${\varphi}_{0}={45}^{\circ}$. The magnitude responses over one normalized FSR of 2π obtained using Eq. (48) for $L=7$ channels (i.e., ${\left|{H}_{k}(\omega )\right|}^{2};k=0,1,\dots ,6.$) are shown in Fig. 3. For ${r}_{0}={R}_{0}=1$, $a[n]=b[n]=c[n]=1$ according to Eqs. (18b), (19b) and (20b), respectively. Hence Design 1 and Design 2 are the same design according to Eqs. (22)-(23). Thus Design 1 is discussed here. It is a straight forward task to compute the values of the parameters shown in Fig. 2 using Eqs. (18b), (18c), (19b), (19c), (20b), (20c) and Eqs. (28)-(37) of Design 1.

## 5. Summary

This paper has presented a simpler architecture of an integrated-optic-based reconfigurable OCZT processor using the simplified CZT algorithm based on the discrete-time convolution method. Compared to the more complex architecture of the reconfigurable OCZT processor in [1], the proposed reconfigurable OCZT architecture is much simpler, requiring much less number of components and eliminating the waveguide crossings that would otherwise make fabrication difficult. The simpler architecture of the proposed reconfigurable OCZT processor makes it even more attractive for future research and development, especially on its numerous potential applications that are yet to be discovered because it is a fundamentally important real-time and high-speed all-optical signal processing device. As a special case of the synthesized OCZT, a novel ODFT design and its potential application as an optical demultiplexer at the receiver of an optical fiber OFDM transmission system has been presented. Is it possible to simplify or reduce the computational complexity of the already-simplified CZT algorithm presented in this work and hence a simpler OCZT architecture? This suggestion is worth considering as a future work.

## References and links

**1. **N. Q. Ngo, “Optical chirp z-transform processor − part I: design,” J. Lightwave Technol. submitted for publication.

**2. **N. Q. Ngo, “Optical chirp z-transform processor − part II: application,” J. Lightwave Technol. submitted for publication.

**3. **J. G. Proakis and D. G. Manolakis, *Digital Signal Processing: Principles, Algorithms, and Applications* (third edition, Prentice Hall, 1996), pp. 152 and pp. 482−483.

**4. **A. V. Oppenheim and R. W. Schafer, *Discrete-Time Signal Processing* (Prentice Hall, 1989), pp. 623−628.

**5. **L. R. Rabiner, R. W. Schafer, and C. M. Rader, “The chirp z-transform algorithm,” IEEE Trans. Audio Electroacoust. **17**(2), 86–92 (1969). [CrossRef]

**6. **L. R. Rabiner, R. W. Schafer, and C. M. Rader, “The chirp z-transform algorithm and its application,” Bell Syst. Tech. J. **48**(5), 1249–1292 (1969). [CrossRef]

**7. **D. Hillerkuss, R. Schmogrow, T. Schellinger, M. Jordan, M. Winter, G. Huber, T. Vallaitis, R. Bonk, P. Kleinow, F. Frey, M. Roeger, S. Koenig, A. Ludwig, A. Marculescu, J. Li, M. Hoh, M. Dreschmann, J. Meyer, S. Ben Ezra, N. Narkiss, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, A. Oehler, K. Weingarten, T. Ellermeyer, J. Lutz, M. Moeller, M. Huebner, J. Becker, C. Koos, W. Freude, and J. Leuthold, “26 Tbits^{−1} line-rate super-channel transmission utilizing all-optical fast Fourier transform processing,” Nat. Photonics **5**(6), 364–371 (2011). [CrossRef]

**8. **K. Takiguchi, T. Kitoh, M. Oguma, Y. Hashizume, and H. Takahashi, “Integrated-optic OFDM demultiplexer using multi-mode interference coupler-based optical DFT circuit,” *Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference**,* OSA Technical Digest (Optical Society of America, 2012), paper OM3J.6. [CrossRef]

**9. **K. Takiguchi, M. Oguma, H. Takahashi, and A. Mori, “Integrated-optic eight-channel OFDM demultiplexer and its demonstration with 160 Gbit/s signal reception,” Electron. Lett. **46**(8), 575–576 (2010). [CrossRef]

**10. **D. Hillerkuss, M. Winter, M. Teschke, A. Marculescu, J. Li, G. Sigurdsson, K. Worms, S. Ben Ezra, N. Narkiss, W. Freude, and J. Leuthold, “Simple all-optical FFT scheme enabling Tbit/s real-time signal processing,” Opt. Express **18**(9), 9324–9340 (2010). [CrossRef] [PubMed]

**11. **K. Takiguchi, M. Itoh, and T. Shibata, “Optical-signal-processing device based on waveguide-type variable delay lines and optical gates,” J. Lightwave Technol. **24**(7), 2593–2601 (2006). [CrossRef]

**12. **Y. Sakamaki, T. Saida, T. Shibata, Y. Hida, T. Hashimoto, M. Tamura, and H. Takahashi, “Y-branch waveguides with stabilized splitting ratio designed by wavefront matching method,” IEEE Photon. Technol. Lett. **18**(7), 817–819 (2006). [CrossRef]

**13. **W. Bogaerts, S. K. Selvaraja, P. Dumon, J. Brouckaert, K. De Vos, D. Van Thourhout, and R. Baets, “Silicon-on-insulator spectral filters fabricated with CMOS technology,” IEEE J. Sel. Top. Quantum Electron. **16**(1), 33–44 (2010). [CrossRef]

**14. **P. Orlandi, F. Morichetti, M. J. Strain, M. Sorel, P. Bassi, and A. Melloni, “Photonic integrated filter with widely tunable bandwidth,” J. Lightwave Technol. **32**(5), 897–907 (2014). [CrossRef]

**15. **N. Q. Ngo, L. N. Binh, and X. Dai, “Optical dark-soliton generators and detectors,” Opt. Comms. **132**(3−4), 389–402 (1996). [CrossRef]