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Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.
© 2014 Optical Society of America
1. Introduction
This work is an extension of the author’s recent article [1]. By direct realization of the CZT algorithm (which is referred to as the non-simplified CZT algorithm), a novel reconfigurable OCZT processor synthesized using the silica-based PLC technology has been presented, to the author’s knowledge, for the first time in [1]. As the first important application of the designed tunable OCZT processor in [1], [2] has presented the design of a tunable ODFT processor (which is a special case of the tunable OCZT processor in [1]) and its application as a tunable optical demultiplexer at the receiver of an optical fiber OFDM transmission system. Several case studies of the author’s novel tunable ODFT-based OFDM demultiplexer have been investigated to demonstrate several of its unique capabilities over the existing non-tunable ODFT-based OFDM demultiplexers [2]. However, in [1], the architecture of the tunable OCZT processor was rather complex because the design was based on the non-simplified CZT algorithm (in which no simplifications were made on the algorithm) that involved a very large number of multiplications and additions. As appeared in Eq. (2), N is the number of input discrete-time samples to be transformed into L number of output frequency samples due to the CZT operation. As such, the number of optical components in the synthesized adaptable OCZT processor was very large (especially when N and L were large) and that there were a number of waveguide crossings or intersections which would make fabrication difficult [1].
To overcome these drawbacks in [1], this paper presents a more simplified CZT algorithm based on the discrete-time convolution method to come up with a much simpler architecture of the tunable OCZT processor design. The simplified CZT algorithm only requires multiplications and additions which are much smaller than those of the non-simplified CZT algorithm in [1], as described above. Hence, it is shown that the number of optical components in the simpler architecture of the tunable OCZT processor in this work is much less than those in [1]. Furthermore, unlike in [1], the adaptable OCZT processor with a simpler architecture in this work has no waveguide crossings or intersections and this will make fabrication much easier. Section 2 presents the simplified CZT algorithm using the discrete-time convolution technique. Using the simplified CZT algorithm, section 3 describes the synthesis of the reconfigurable OCZT processor with a simpler architecture using the silica-based PLC technology. Section 4 presents the design of an ODFT as a special case of the synthesized OCZT and its potential application. Conclusion is given in Section 5.
2. Simplified CZT algorithm
This section presents a simplified CZT algorithm based on the discrete-time convolution technique [3–6]. An input analog complex-valued signal is sampled at the sampling period T (or unit-time delay of a filter) to yield a discrete-time N-point sequence so that (see Fig. 4(a) of [1]). The unilateral N-point z-transform of is given by [3–6]
where the z-transform parameter is defined as , where and is the angular frequency. It is assumed that the sum in Eq. (1) converges for all z except at z = 0. In Eq. (1), is transformed into its complex-plane representation which is the spectrum of . By computing Eq. (1) at a set of L equally-spaced frequency samples on an arbitrary contour in the z plane, i.e., the L output frequency samples are given by [3–6]where N and L are arbitrary integers andwhere , , and and are positive real numbers. The variables in Eq. (3) have been defined in [1]. The non-simplified CZT algorithm is described by Eqs. (2)-(3) [1]. Figure 1 of [1] shows the graphical meaning of Eq. (3). A plot of Eq. (3) for several case studies is shown in Fig. 2 of [1]. The simplified CZT algorithm derived using the discrete-time convolution technique is described as follows. Putting Eq. (3) into Eq. (2), the CZT of is given by [3–6]wherePutting the ingenious identityinto Eq. (4) giveswhereThe use of the elegant identity defined in Eq. (6) makes it possible to express Eq. (4) (which is called the non-simplified CZT algorithm [1]) into a form that involves the convolution operation and hence the derivation of the simplified CZT algorithm, as explained next. To express Eq. (7) as a convolution, replace k by n and n by k in Eq. (7) to giveLet Putting Eq. (10b) into Eq. (9) giveswhere where * denotes the convolution operation. Equations (12a) and (12b) mean that the output discrete-time sequence is given by the discrete-time convolution of an input discrete-time sequence with the discrete-time impulse response of a linear time-invariant system which is here a finite-impulse response (FIR) filter. Then is multiplied by the sequence to give the CZT output according to Eq. (11). In Eqs. (11) and (12a), the range of is and the ranges of both and are Using these results, it can be easily shown from Eq. (12a) that the range of in Eq. (10a) is given by . HenceIn Eq. (13), corresponds to the right number (i.e., no more and no less) of filter coefficients in the impulse response , avoiding the use of extra or redundant filter coefficients for structural simplicity. In Eq. (13), corresponds to a non-casual filter which is not practical for real-time implementation. To make a casual impulse response for real-time implementation delay by samples to become and a new variable is thus defined as . Substituting this expression into Eq. (13) givesNote that in in Eq. (13) has been changed to in in Eq. (14) because has been delayed by samples to give . Putting from Eq. (14) into Eqs. (12a) and (12b) gives Since in Eq. (13) and hence Eq. (12) have been delayed by samples, in Eq. (12) must also be delayed by the same samples because in Eq. (12) remains unchanged. Hence, in Eqs. (15a) and (15b), for because in Eq. (14) also has . Since has been delayed by samples according to Eq. (15), , the chirp factor and in Eq. (11) must also be delayed by the same samples such thatSince in Eq. (16) has been delayed by samples, the L useful (or correct) output frequency samples correspond to the samples of that are samples in advance such thatEquation (8) can be written aswhere Putting Eq. (5) into Eq. (14) giveswhere Putting Eq. (5) into Eq. (16) giveswhere Note that Eq. (20d) is the same as Eq. (17). Equation (20a) gives all (i.e., ) the output frequency samples. However, the L useful output frequency samples are according to Eq. (20d) while in Eq. (20a) are the redundant or non-useful output frequency samples which should not be implemented to simplify the architecture. In summary, Eqs. (18a), (15a), (15b), (19a), (20a) and (20d) describe the simplified CZT algorithm using the discrete-time convolution method and its block diagram representation is shown in Fig. 1. The FIR filter with an up-chirp impulse response defined in Eq. (19a) is called a chirp filter for the following reason. The algorithm is called the simplified chirp z-transform (CZT) algorithm because is a complex exponential sequence with linearly increasing frequency. These kinds of signals (or impulse responses) are called chirp signals (or impulse responses) in radar systems and hence the name chirp in the simplified CZT algorithm [3–6]. Hence the FIR filter with defined in Eq. (19a) is called the chirp filter. Radar and sonar signal processing systems similar to the simplified CZT system shown in Fig. 1 have been widely used for pulse compression [3–6]. The simplified CZT algorithm basically consists of three operations in the following sequential order (see Fig. 1): (i) pre-multiply down chirp; (ii) convolution; and (iii) post-multiply down chirp. Down chirp means that there is a negative sign in [Eq. (18c)] and also in [Eq. (20c)] while up chirp means that there is a positive sign in [Eq. (19c)].
Fig. 1 Block diagram representation of the simplified CZT algorithm using the discrete-time convolution method.
Fig. 2 Schematic diagram of the synthesized reconfigurable OCZT processor using the silica-based PLC technology. TC: tunable coupler; PS: tunable phase shifter; DC: directional coupler; and EDFA: erbium-doped fiber amplifier. (a) Tunable coupler (TC). (b) g[n], as defined in Eqs. (18), (32) and (33). The gates (or samplers), as shown, are for illustration only and should be removed when fabricating the device. These gates are moved to Fig. 2(d) for structural simplicity, without affecting the device performance. (c) y[n], as defined in Eqs. (15), (19), (34) and (35). (d) , as defined in Eqs. (26), (36) and (37), and as defined in Eq. (20d).
3. Synthesis of a reconfigurable OCZT processor with a simplified architecture
Using the simplified CZT algorithm described in Section 2, this section presents the synthesis of a reconfigurable OCZT processor using the silica-based PLC technology [7–12]. Other integrated-optic technologies (e.g., the silicon-on-insulator (SOI) platform which is compatible with the complementary metal-oxide-semiconductor (CMOS) technology) could also be employed for the implementation of the reconfigurable OCZT processor [13,14]. Two designs of the tunable OCZT processor based on the same architecture are presented here to cater for different application requirements. The optical synthesis of and is described as follows. As explained in the texts below Eq. (27b) and also in Eq. (33), the phase angle defined in Eqs. (18a) and (18c) can be realized using a thermo-optic-based tunable phase shifter (PS) [7–11]. While the amplitude defined in Eqs. (18a) and (18b) can be realized using a thermo-optic-based tunable coupler (TC) with a coupling coefficient of between 0 and 1 (inclusive) [7–11, 15]. Applying on Eq. (18b) gives
orNote here that has been designed to be in the range of (rather than ) so that it can be realized using a TC, eliminating the need to use an optical gain element which will be much more difficult to fabricate. Comparing Eq. (19b) with Eq. (20b) givesfrom which two possible designs are These designs have and they are described in Sections 3.1 and 3.2, respectively.3.1 Design 1:
In this Design 1, applying on Eq. (19b) gives
Applying Eq. (24) on Eq. (21a) givesThis Design 1 requires , and to avoid using an optical gain element to realize , the following approach is employed. Also, cannot be implemented using a TC with a coupling coefficient of between 0 and 1 (inclusive) unless in Eq. (20a) is normalized. Thus, normalize in Eq. (20a) to givewhere () is the maximum value of and where . Now can be implemented using a TC with a coupling coefficient of between 0 and 1 (inclusive), and this is the same situation as , as described above. The optical synthesis of and using the TC is explained below. In Eq. (26), can be implemented using gain provided by an erbium-doped fiber amplifier (EDFA), as explained below.Using Eqs. (18a), (15a), (15b), (19a), (20a) and (20d) and Fig. 1, Fig. 2 shows the schematic diagram of the synthesized reconfigurable OCZT processor based on the silica-based PLC technology. Without loss of generality, the waveguide loss is neglected for ease of analysis. In Fig. 2(b), in assigning the notations at the inputs of the block, the splitting loss of the splitter in the serial-to-parallel converter is ignored for ease of analysis. Similarly, in Fig. 2(d), in assigning the notations at the inputs of the block, the splitting loss of the splitter in the serial-to-parallel converter is neglected for ease of analysis. However, these splitting losses will be taken into consideration below as shown in Eq. (27). The serial-to-parallel converters and the samplers shown in Figs. 2(b) and 2(d) are described below. The splitters and combiners in Figs. 2(b)-2(d), which consist of the cascade of Y-branch waveguides arranged in a binary fashion, can be designed using the wavefront matching method [12]. This type of splitter/combiner is better than a slab splitter/combiner, including a star coupler and a multi-mode interference (MMI) splitter/combiner, in terms of the uniformity of the splitter ratio [8]. To compensate for the splitting losses of the three splitters in Figs. 2(b)-2(d), the two G terms (the intensity gains) are provided by an EDFA at the input and another EDFA at each output:
where is the splitting loss of the splitter in Fig. 2(b), is the splitting loss of the splitter in Fig. 2(c), and is the splitting loss of the splitter in Fig. 2(d). In Fig. 2(a), the tunable PS is a thin-film heater loaded on the waveguide and utilizes the thermo-optic effect to induce a phase change of the optical carrier by [7–11]. The PSs are used in Figs. 2(b)-2(d). In Fig. 2(a), the TC is a symmetrical Mach-Zehnder interferometer that consists of two 3-dB directional couplers (DCs), two waveguide arms of equal length and a thin-film heater, with a carrier phase change of , deposited on one of the arms for controlling the desired coupling coefficient [7–11], [15]. The TCs are used in Figs. 2(b)-2(d). The OCZT processor is reconfigurable due to the tunable features of the tunable PSs and TCs. The TC’s transfer function is given by [15]The desired TC’s coupling coefficient is given bywhich can be controlled to a desired value by adjusting the phase shift value of the tunable PS according toAccordingly, the TC’s output phase is given byThe coupling coefficient and output phase of the TC, both of which repeat themselves at every cycle of 2π, can be continuously tuned from 0 to 1 (inclusive) and from to 0, respectively, when is varied from 0 to [15]. The optical synthesis of and in Eq. (18) and Fig. 2(b) is explained as follows. From Fig. 2(b), in Eq. (18b) is given bywhere . From Fig. 2(b), in Eq. (18c) is given bywhere . Similarly, the optical synthesis of and in Eq. (19) and Fig. 2(c) is described as follows. From Fig. 2(c), in Eq. (19b) is given bywhere . in Fig. 2(c) relates to in Eq. (19c) according towhere . Similarly, the optical synthesis of in Eqs. (26) and (20b) and in Eq. (20c) and Fig. 2(d) is explained as follows. From Fig. 2(d), in Eq. (26) is given bywhere . in Fig. 2(d) relates to in Eq. (20c) according towhere .3.2 Design 2:
In this Design 2, just like Design 1 described in section 3.1, , and and in Fig. 2(b) are described by Eqs. (32) and (33), respectively. In this Design 2, and applying this condition on Eq. (19b) gives
Applying Eq. (38) on Eq. (21a) givesSince in this Design 2 cannot be realized using a TC with a coupling coefficient of between 0 and 1 (inclusive), normalize in Eq. (19a) to givewhere , is the maximum value of and where . Now can be implemented using a TC, and this is the same situation as in Design 1. In Fig. 2(c), the notation for Design 1 must be changed to for Design 2 according to Eq. (40). Hence where and . Also, in Fig. 2(d), the notation for Design 1 must also be changed to since for Design 2. Thus where and . Similarly, in Eq. (27b), replacing for Design 1 with for Design 2 givesIn Fig. 2(b), the N input discrete-time samples at the inputs of the block can be generated using a serial-to-parallel converter and N gate-based optical samplers [7–10]. Together with the serial-to-parallel converter, the optical gates (or samplers) must synchronously sample the input continuous-time signal over the time slot and convert it into its discrete-time representation [Fig. 2(b)]. The optical gates can be implemented using electro-absorption modulators (EAMs) [7–10]. In Fig. 2(b), is equally split (by a splitter) into N signals which are relatively delayed (using delay lines in the delay array 1) by integer multiples of T and then time gated (by the optical samplers) so that the discrete-time samples will arrive at the respective input ports of the block at the same time slot of T to achieve time synchronization according to Eq. (18a). In the delay array 1, the top waveguide has the largest delay of to slow down most because it is the fastest sample. Conversely, the bottom waveguide has the smallest delay to speed up most because it is the slowest sample. As such, all the samples will simultaneously arrive at the inputs of the block at the same time slot of T. In the delay array 2 of the block, the delay lines differ by integer multiples of T so that the neighbouring samples of at the output of the combiner are separated by T. in the block implement Eqs. (32) and (33), respectively, and thus the block is realized. However, to fabricate the whole device on the silica-based PLC platform, the optical gates shown in Fig. 2(b) are moved to the output ports of the tunable OCZT processor as shown in Fig. 2(d), without affecting the device characteristics due to its linearity property. The FIR filter shown in Fig. 2(c) is the implementation of Eqs. (15), (19), (34) and (35). In Fig. 2(d), the block implements Eqs. (26), (36) and (37) and relates to according to Eq. (20d). Similar to the function of the serial-to-parallel converter in Fig. 2(b), the input discrete-time samples (which are some of the FIR filter’s total output time samples in Fig. 2(c)) at the input of the serial-to-parallel converter in Fig. 2(d) are equally split (by a splitter) into discrete-time samples which are relatively delayed (using the delay lines in the delay array 1) by integer multiples of T so that will arrive at the respective input ports of the block at the same time slot of T to achieve time synchronization according to Eqs. (26) and (20d). In the delay array 1, the top waveguide has a larger delay of to slow down more because it is a faster sample. Conversely, the bottom waveguide has the smallest delay to speed up most because it is the slowest sample. As such, all the samples will simultaneously arrive at the respective input ports of the block at the same time slot of T. In the delay array 2 of the block, the delay lines differ by integer multiples of T so that defined in Eqs. (26) and (20d) can be realized. At the outputs, the L useful output frequency samples are according to Eq. (20d). To obtain time synchronization so that all the input time samples in Fig. 2(b) propagate in synchronism from one stage to the next, the waveguides (on which the TCs and PSs are placed) and the Y-branch waveguides inside the splitters and combiners must have the same delay. As such, the L useful output frequency samples will simultaneously appear at the respective output ports (i.e., before the gates and the EDFAs) of the tunable OCZT processor at the same time. Furthermore, on each waveguide path, the TC’s coupling coefficient can also be adjusted to compensate for any non-uniform splitting ratio of the splitters and also for any non-uniform combining ratio of the combiners. On each waveguide path, the PS’s phase shift value can also be adjusted to be slightly more or less (if needed) than the designed value to compensate for any length deviation due to fabrication error of the waveguide path. A waveguide can be fabricated to the precision of 1 μm using the silica-based PLC technology [11].
From Table 1, it is clear that the proposed tunable OCZT architecture is much simpler than that reported in [1]. The choice of the L and N values depends on the application requirements [1,2].
Table 1. The Tunable OCZT Architecture using the Simplified CZT Algorithm in this paper is Much Simpler than that using the Non-simplified CZT Algorithm Reported in [1]
One important application example of the proposed tunable OCZT processor based on the simplified CZT algorithm is described as follows. As explained in [1] (see Fig. 2(b) of [1]) and [2] (see sections 2 and 3 and Table 1 of [2]), by putting into Eq. (3) (it is also Eq. (3) in [1,2]), a new tunable ODFT processor can be designed as a special case of the tunable OCZT processor based on the non-simplified CZT algorithm. The ODFT processor is tunable because and in Eq. (3) can be continuously tuned to be within and , respectively. While the current non-tunable ODFT processors designed using the fast Fourier transform (FFT) algorithm [7–10] also have but and cannot be tuned and must take the fixed values of and with (see Fig. 2(a) of [1]). As such, the current non-tunable ODFT processors (such as those described in [7–10]) are a special case of the tunable ODFT processor of [1,2]. Table 1 of [2] provides a summary of the unique advantages of the tunable ODFT processor based on the non-simplified CZT algorithm over the current non-tunable ODFT processors designed using the FFT algorithm. These unique advantages over the current non-tunable ODFT processors are also enjoyed by the proposed tunable ODFT/OCZT processor based on the simplified CZT algorithm in this work. The only difference is that the proposed tunable OCZT processor based on the simplified CZT algorithm here has a simpler architecture than that of the tunable OCZT processor based on the non-simplified CZT algorithm in [1,2].
4. A design example and its potential application
This section presents the design of a new type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT presented in Section 3 to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system [7–10]. Putting (as required by an ODFT) into Eqs. (4)-(5) gives
where , , and . In the continuous-time domain, Eq. (46) is given aswhere is the Dirac delta function, denotes the convolution operation, , , and FT denotes the Fourier transform operation. Taking the FT of Eq. (47), the transfer function of a novel type of ODFT (for the kth output frequency sample ; ) is given byIn the conventional ODFTs, , , , and [7–10]. In the new ODFT presented here, ; however N and L are arbitrary integers, can be chosen to be within , and can be chosen to be within provided that to avoid overlapping of the neighbouring channels in the magnitude response. The chosen values of and must satisfy the fact that the L channels must lie within one normalized free spectral range (FSR) of 2π. Hence, the conventional ODFTs [7–10] are a special case of the new ODFT. As a design example, the new ODFT has , , , , and . The magnitude responses over one normalized FSR of 2π obtained using Eq. (48) for channels (i.e., ) are shown in Fig. 3. For , according to Eqs. (18b), (19b) and (20b), respectively. Hence Design 1 and Design 2 are the same design according to Eqs. (22)-(23). Thus Design 1 is discussed here. It is a straight forward task to compute the values of the parameters shown in Fig. 2 using Eqs. (18b), (18c), (19b), (19c), (20b), (20c) and Eqs. (28)-(37) of Design 1.Fig. 3 Magnitude response of the new ODFT design as a special case of the synthesized OCZT with , , , , and .
5. Summary
This paper has presented a simpler architecture of an integrated-optic-based reconfigurable OCZT processor using the simplified CZT algorithm based on the discrete-time convolution method. Compared to the more complex architecture of the reconfigurable OCZT processor in [1], the proposed reconfigurable OCZT architecture is much simpler, requiring much less number of components and eliminating the waveguide crossings that would otherwise make fabrication difficult. The simpler architecture of the proposed reconfigurable OCZT processor makes it even more attractive for future research and development, especially on its numerous potential applications that are yet to be discovered because it is a fundamentally important real-time and high-speed all-optical signal processing device. As a special case of the synthesized OCZT, a novel ODFT design and its potential application as an optical demultiplexer at the receiver of an optical fiber OFDM transmission system has been presented. Is it possible to simplify or reduce the computational complexity of the already-simplified CZT algorithm presented in this work and hence a simpler OCZT architecture? This suggestion is worth considering as a future work.
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