## Abstract

This paper presents and demonstrates the three logic processing levels based on complementary photonic crystal logic devices through photonic integrated circuit modeling. We accomplished a set of logic circuits including AND, OR, NAND, NOR, XOR, FAN-OUT, HALF ADDER, and FULL ADDER based on photonic crystal slab platforms. Furthermore, we achieved efficient all-optical logic circuits with contrast ratios as high as 5.5 dB, demonstrated in our simulation results, guaranteeing well-defined output power values for logic representations; a clock-rate up to 2 GHz; and an operating wavelength at *λ* ≈ 1550 nm. Thus, we can now switch up for high computing abstraction levels to build photonic integrated circuits rather than isolated gates or devices.

© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

## 1. Introduction

The physical limitation of conventional CMOS transistors miniaturization and the consequent downfall of Moore’s Law have motivated an ongoing pursuit for emerging technologies to aid the development of computational systems able to support the demands of deep learning, big data, internet-of-things (IoT), autonomous driving, datacenters, cryptocurrencies, wearable systems, neuromorphic computing, and many other applications [1–5]. Low power consumption, high speed of data processing, and low energy dissipation are the main desirable features for the new generation of computers [6,7].

Photonics is an emerging technology capable of fulfilling digital electronics gaps and achieving the desired features mentioned before. Since its discovery and demonstration, Photonic Crystals (PhCs) appear as a promising platform to realize the fully optical processing information and computing [8–11]. The PhC ability to control electromagnetic waves, compactness, low power consumption and exceptional confinement of light has opened a large variety of applications for telecommunications, signal processing, biophotonics, and computing [12–16].

Within the domain of logic devices and circuits, some advances have been achieved based on different approaches. Examples of that are: logic gates based on self-collimation effects, multi-mode interference, waveguide interference paths, ring resonator, four-wave mixing, temporal solitons and nonlinear effects [17–32]. Despite the technological advances achieved in this area of knowledge, limitations to creating logical systems are evidenced due to the inability to concatenate gates to project circuits. The main obstacles identified are unequal input and output wavelengths, different power values to represent the same logic state, high input powers to achieve nonlinear effects, and weak output response [7,31,33]. We recently proposed Complementary Photonic Crystal Integrated Logic (CPCL) switches, aiming to cascade devices and build circuits [33]. This is a fundamental step towards the development of a completely photonic logic.

Considering the above, we applied the CPCL to address and demonstrate how PhC logic gates and circuits can be implemented by the adjacent connection of the proposed Switches N and P. Furthermore, our work solves some of the aforementioned drawbacks allowing us to project PhC universal integrated logic circuits rather than isolated devices or components. It means that we can now design any computational circuit for a wide range of applications by applying a similar methodology to the well-known and mature CMOS technology. This is a key point towards the realization of all-optical systems switching up from isolated components to circuits and reaching high computing abstraction levels. Thus, we perform reliable Finite-Difference Time-Domain (FDTD) simulations through the Lumerical FDTD Simulation tool to prove a complete set of logic gates and circuits including AND, OR, NAND, NOR, XOR, FAN-OUT, HALF-ADDER, and FULL-ADDER components. Furthermore, these PhC gates and circuits operate with the same input and output wavelength, have well-defined output power values to represent the logic states 0 and 1, and exhibit an ON-OFF contrast ratio higher than 5.50 dB. So, we ensure that our circuits achieve the main features to obtain practical devices for fabrication, enabling large-scale circuit integration [7]. In accordance with what was previously described, the results presented in this work open up new possibilities for future research on PhC logic circuits and systems.

This manuscript is organized as follows: In Section 2 we present the study of the input and output power values for the CPCL. In Section 3 we address how CPCL is used to model PhC logic gates and circuits and provide numerical simulations to demonstrate it. Section 4 discuss the main results of this work and compare them with the most recent advances in this field. Finally, Section 5 gathers the main conclusions.

## 2. Photonic crystal switches N and P

We previously proposed the Complementary Photonic Crystal Logic Devices (CPCL) [33], where the efficient operation of the Switch N (SwN) and Switch P (SwP) were demonstrated. These devices are PhC equivalents to the NMOS and PMOS transistor of the CMOS technology.

As a rule of thumb, our adopted PhC configuration is composed of a triangular lattice of holes embedded in a dielectric heterostructure substrate of GaAs/AlGaAs with effective refractive index $n_{eff}=2.87$. The heterostructure consists of a 500 nm GaAs core with 180 nm of Al$_{0.25}$Ga$_{0.75}$As cladding on top and downsides, and a 1500 nm buffer of Al$_{0.6}$Ga$_{0.4}$As. Its $n_{eff}$ was theoretically derived by performing an extensive modal analysis which ensures single-mode propagation and strong confinement of the fundamental TE00 mode. The radius of holes and the lattice constant are 130 nm and 420 nm, respectively. The aforementioned configuration obtained for the PhCs guarantees a photonic bandgap between 1290 nm to 1670 nm. The complete design of the slab heterostructure is detailed in Ref. [33].

The SwN is composed of four terminals, called Input (In), Control (C), Output (O), and Drain (D). Its logic Output will have the same Input value if the Control is 1. Otherwise, it will be 0, as shown in Figure 1(a). We proved the operation of our PhC integrated SwN at $\omega _{op}=$ 193.45 THz of input and output operating frequency by setting up output power values greater than 50 mW and lower than 10 mW as logic 1 and 0, respectively [33]. On the other hand, the SwP is exactly the opposite of the SwN. Specifically, its logic Output will be the same as the Input if the Control is 0. Otherwise, it will be 0, as illustrated in Figure 1(b). The output power values obtained to represent the logic 1 and 0 were greater than 42 mW and lower than 12 mW, respectively [33].

Here we introduce a wide study of the switches output power responses to better describe the systems and achieve a proper setup for each PhC integrated gate and circuit. Therefore, we perform a set of simulations consisting of all the setups for the Input and Control sources from 0 to 80 mW with power steps of 5 mW.

Figure 2 shows the output power response as a function of each Input and Control combination for both the Output and Drain of SwN. We can observe in Figure 2(a) that the greater the Input and Control, the greater the power value at the Output of SwN, reaching a power value of about 118 mW for the SwN(80,80) input setup. This result shows that the SwN operates as an optical amplifier since we can modulate the power at the Control to achieve the desired power value to represent a specific logic state. Figures 2(b) also shows an increase in the Drain value, but it is much smaller and can be neglected since it is not used in the logic datapath.

In the same direction, Figure 3(a) illustrates how the SwP output power changes as a function of the applied Input and Control signals. To represent the PMOS transistor, the Output is on only when the input is on, but the Control is off. Thus, for this instance, when the input setup SwP(80,0) is performed, the SwP Output achieves its maximum value, i.e., 63 mW. However, once the Control signal increases, the Output is turned off, decaying to a value of about 12 mW when the input setup SwP(80,80) is carried out. This fact demonstrates the ability of the SwP to operate as a signal reducer by applying the correct power signal at the Control source. Finally, Figure 3(b) shows the Drain power, which is also neglected in the circuits.

## 3. Modeling of the integrated logic gates and circuits

For the design of the gates and circuits applying the switches, we adopt the Finite-Difference Time-Domain (FDTD) method using the Lumerical FDTD Solution Tool to demonstrate the correct operation of the PhC circuits, thus ensuring accurate and reliable numerical simulations. First, we set the simulation Courant stability condition in 0.7 with a time step of 0.04 fs and space step of 0.02 $\mu m$. The Perfectly Matched Layer (PML) has a thickness of the order of the operating wavelength, i.e., about 1550 nm. Then, we divide the simulation space into three sections: Input (IS), PhC Processing Logic Unit (PPLUS), and Output (OS), as graphically described in Figure 4.

In the IS, we place all input sources and input waveguides. So, to represent logic 1, we use a 50 mW Gaussian pulse centered at 193.41 THz (1550 nm) and a full-width of 0.24 THz. On the other hand, the absence of a light signal means logic 0. It is important to clarify that we define an Adapted Source Power (ASP), which is an adjustable reference signal to modulate the optical power levels into the system, maintaining the expected performance at the output. Its power value is derived empirically, and we will detail it below for each circuit. The PPLUS is the core of the circuit and where the logic takes place. In this sense, we string the Switches N and P to obtain the desired logic function at the output of our system. Finally, in the OS, we place the output waveguides and the field and power monitors. These monitors collect the field profile in the frequency domain from simulation results across some spatial region within the simulation in the FDTD. Essentially, the E (Electric field), H (Magnetic field), P (Poynting vector) and T (Transmission) as a function of frequency are calculated by applying a Fourier transform on the simulation time collected data. Here, we capture the intensity distribution at the steady-state at $\omega _{op} = 193.45$ THz. In addition, we compute the power value at the output waveguides. Aiming to optimize the computational resources, the monitoring of the intensity distribution system will be carried out in OS. Later, we analyze the performance of our system, transforming the power response into a logic response. So, we define a high logic threshold ($P_{1}$) and power values to represent logic 1. In contrast, power values below the lower threshold ($P_{0}$) will represent the logic 0. Then, we proceed to calculate the ON-OFF contrast ratio (CR) of the device, as follow:

Following, we present the AND, OR, NAND, NOR, and XOR logic gates, plus the wire split FAN-OUT and the Half Adder and Full Adder circuits. It is important to highlight that all these logic gates and circuits are composed exclusively of switches N and P, our basic devices.

#### 3.1 AND

A Switch N by itself can already be used as an AND gate. However, as one of the main goals of this work is to study cascaded switches, we designed a logic circuit based on two PhC SwNs connected in series. The resulting system has three inputs and three outputs terminals, as represented in Figure 5(a). In this, the ASP represents a fixed input with logic value 1. The resulting logic function for the Output (O) can be described as follow:

where A and B are the logic inputs. Thus, the logic output terminal of this circuit will be 1 only when the outputs of the two SwNs are 1. Otherwise, it will be 0. This system is equivalent to the AND logic function, O = A$\cdot$B.Figure 5(b) shows the schematic representation of the designed PhC integrated AND circuit. It has a footprint area of $37.38~\mu m \times 16.00~\mu m$. At this point, we set the ASP at 30 mW, which is a suitable value to achieve the desired logic states at the output. Figures 6(a-d) illustrate the OS normalized intensity distribution of the optical propagating mode of the PhC integrated AND circuit at the steady-state for the complete set of input combinations. The normalization rule consists of scaling the intensity by a factor $\delta =1/max(A_{h})$, where $max(A_{h})$ is the maximum value of the intensity distribution with the higher output power. For this instance, $max(A_{h})$ is obtained when the logic operation AND(1,1) = 1 is carried out. With this information, we can set power values greater than 50 mW and lower than 12 mW as logic 1 and 0, respectively. These values mean a CR of 6.19 dB for this gate. It also presents a clock rate of 12.5 GHz since it reaches the steady-state at 80 ps. The Drain outputs are disregarded. Thus, we demonstrate the correct operation of the PhC integrated AND gate.

#### 3.2 OR

Our OR logic gate is based on a parallel arrangement of two SwNs, as represented in Figure 7(a). The logic output for this circuit is:

where A and B are logic inputs, while $J$ represents the function of a PhC Y-junction. For this kind of PhC device, we found that the output power response is about 84% of the total input power applied. Thus, the logic output terminal (O) of the circuit will be 1 if any output of the SwNs is 1. Similarly, it will be 0 only when both of the SwNs outputs are 0. It is the equivalent circuit to the OR logic function, i.e., O=A$+$B.Figure 7(b) illustrates the design of the PhC structure equivalent to the OR circuit, with a footprint of $31.50~\mu m \times 20.36~\mu m$. Since the ASP path is split to both SwNs, we set its power at 80 mW. It is important to note that our PhC splitter divides the input power into two branches with about 43% each. Figures 8(a-d) show the OS normalized intensity distribution of the optical propagating mode for our OR circuit at the steady-state for the complete set of input combinations. So, we can appreciate that power values greater than 44 mW and lower than 6 mW represent logic 1 and 0, respectively. These values show a CR of 8.65 dB for this circuit. It also exhibits a clock rate of 12.5 GHz.

#### 3.3 NAND

Aiming to obtain an all-optical NAND logic gate, we connect a SwN to a SwP, as can be seen in Figure 9(a), and whose logic output behavior can be described by (4).

The output of the PhC integrated NAND gate will be 0 when the output of SwN is 1; otherwise, it will be 1. Thus, it is analogous to the NAND logic function, represented by O = $\neg$(A$\cdot$B). The designed PhC structure for this circuit has a footprint area of $37.50~\mu m \times 18.91~\mu m$, and its representative scheme can be seen in Figure 9(b). For this instance, we set the power value of the ASP at 70 mW. Figures 10(a-d) show the OS normalized intensity distribution of the optical propagating mode of the PhC integrated NAND circuit at the steady-state for the complete set of input combinations. Thus, power values greater than 45 mW and lower than 12 mW stand for logic 1 and 0, respectively. These values mean a CR of 5.74 dB for this circuit. It also presents a clock rate of 12.5 GHz, reaching its steady-state at 80 ps.

#### 3.4 NOR

Towards the realization of the PhC NOR logic gate, we connect two SwPs in series, as illustrated in Figure 11(a). The resulting system leads to a logic output described by the following equation:

Thus, we obtain an equivalent to the NOR logic function, O = $\neg$(A$+$B), since the circuit output will be 1 only if both SwPs outputs are 1. Otherwise, it will be 0.

Figure 11(b) shows the designed structure for the PhC integrated NOR circuit, which has a footprint of $31.08~\mu m \times 21.82~\mu m$. In this case, we set the ASP at 60 mW. Figures 12(a-d) show the OS normalized intensity distribution of the optical propagating mode of the PhC integrated NOR circuit at the steady-state for its input combinations. Power values greater than 47 mW and lower than 12 mW indicate logic 1 and 0, respectively. These values show a CR of 5.92 dB. This circuit also exhibits a clock rate of 12.5 GHz.

#### 3.5 XOR

We achieve a PhC XOR logic gate by connecting two SwPs in parallel. The description of the logic output for our XOR circuit is given by:

where the logic output will be 1 if any output of the SwPs is 1, otherwise it will be 0. It is the equivalent circuit to the XOR logic function, i.e., O = A$\oplus$B. It is important to note that the inputs signals swap for each SwP. Indeed, input A serves as the Input for the first SwP and the Control for the second SwP. In the opposite direction, input B operates as the Control for the first SwP and as the Input for the second SwP. This fact implies that an intersection path occurs between the input signals generating interference between the PhC waveguides. The correct operation and the performance of the PhC XOR circuit can be affected due to the 2D nature of our structure and mainly by the absence of a cross information device that avoids the previously mentioned interference signals. Thus, we adopt a simplified dual-rail strategy consisting of replicating the input signals to prevent the undesired interference and intersection between the input sources. Figure 13(a) shows the diagram of the final setup to achieve the PhC integrated XOR circuit.Figure 13(b) illustrates the simulated structure for the PhC integrated XOR circuit, which has a footprint of $27.30~\mu m \times 24.73~\mu m$. Furthermore, Figures 14(a-d) show the OS normalized intensity distribution of the optical propagating mode at the steady-state for the complete set of input combinations of this circuit. Accordingly, we set power values up to 43 mW and down to 3 mW to represent logic 1 and 0, respectively. These values mean a CR of 11.56 dB for this circuit. It also presents a clock rate of 12.5 GHz.

#### 3.6 FAN-OUT

In this section, we implemented a circuit to split a signal in two without losing value. This is a fundamental device to drive logic gates connections in a circuit. It was designed based on two SwNs, as can be seen in Figure 15(a), where the logic functions for each output (O1, O2) are described as follow:

Since the ASP will always be high, the output O1 and O2 will be 1 if the Input (In) is 1. Otherwise, they will be 0.

Our simulated structure for the PhC integrated FAN-OUT circuit is illustrated in Figure 15(b). It has a footprint area of $26.46~\mu m \times 20.36~\mu m$. To achieve the desired power representations for logic 1 and 0 at the outputs, we set the ASP as 50 mW, which is enough power amount. Overall, Figure 16(a) and 16(b) show the OS normalized intensity distribution of the optical propagating mode at the steady-state for the complete set of input combinations. So, we define power values greater than 48 mW and lower than 7 mW as logic values 1 and 0, respectively. These values show a CR of 8.36 dB. This circuit has a clock rate of 12.5 GHz.

#### 3.7 HALF ADDER

The half-adder (HA) is a circuit that adds two single binary digits (A and B) and produces two outputs (Sum and Carry), as can be observed in Figure 17(a). The resulting Carry and Sum are generated from the AND and XOR logic operations, respectively. HAs are commonly used in computers and microprocessors in the Arithmetic Logic Unit (ALU). As mentioned before, in Section 3.5, due to the absence of a cross-information device, we replicated the input signals.

The PhC structure for the HA circuit with a footprint of $27.30~\mu m \times 32.00~\mu m$ is presented in Figure 17(b). The OS normalized intensity distributions of the optical propagating mode at the steady-state for all input combinations are shown in Figures 18(a-d). Input and output power values are the same as the AND and XOR logic circuits. So, we can represent power values greater than 43 mW and lower than 12 mW as logic 1 and 0, respectively. These values indicate a CR of 5.54 dB for this circuit. The PhC integrated HA presents a clock rate of 12.5 GHz.

#### 3.8 FULL ADDER

The Full-Adder (FA) is a combinational circuit based on three inputs and two outputs, which computes the binary sum of two arbitrary numbers. It solves the limitation of the HA to handle the carry bit from the addition of two previous digits. So, we can string FAs together to create a byte-wide adder and cascade the carry bit from one FA to the next. In this work, for practical considerations and to reduce the computational cost to perform the simulations, we divided the PhC FA into two circuits, the CARRY, and the SUM, which are explained in the following sections.

### 3.8.1 CARRY

Our PhC-based Carry circuit for the FA has three logic inputs and one logic output (C$_{out}$), as follows:

where A, B are the two binary digits and C$_{in}$ is the carry bit. In the Figure 19(a), it is possible to appreciate the CPCL circuit equivalents to the FA Carry circuit.Figure 19(b) shows our designed structure for the PhC integrated FA Carry circuit, which has a footprint of 44.94 $\mu$m $\times$ 33.46 $\mu$m. For this circuit, we set the ASP as 50 mW. The OS normalized intensity distribution of the optical propagating mode for all input combinations at the steady-state of the circuit is illustrated in Figures 20(a-h). At this point, it is important to mention that the PhC Carry circuit achieves its steady-state at 100 ps. Also, power values greater than 44 mW and lower than 12 mW stand for logic 1 and 0, respectively. These values indicate a CR of 5.64 for this circuit. The obtained clock rate for the FA Carry circuit is 10 GHz.

### 3.8.2 SUM

Here, we detail the PhC Sum circuit for the FA. It consists of three inputs and one output, named S$_{um}$. By using the CPCL, we can calculate its logic output through the following equation:

where A, B are the two binary digits, and C$_{in}$ is the carry bit. Figure 21(a) represents the CPCL circuit equivalents to the FA Sum circuit.The simulated structure for the PhC integrated FA Sum circuit, which has a footprint of 74.97 $\mu$m $\times$ 45.10 $\mu$m, is illustrated in Figure 21(b). We set ASP A and B for this circuit with 30 mW and 50 mW, respectively. So, we can appreciate in Figures 22(a-h) the OS normalized intensity distribution of the optical propagating mode for all input combinations at the steady-state. From this information, we can define power values up to 44 mW and down to 12 mW as the logic 1 and 0, respectively. These values mean a CR of 5.64 dB for this circuit, and a clock rate of 8.3 GHz is also obtained.

## 4. Discussion

The PhC logic devices have received great attention during the last years due to their relevance for the development of all-optical computational circuits. In this way, different strategies have been successfully applied to design logic gates on PhC platforms, including self-collimation effects, multi-mode interference, waveguide interference paths, ring resonator, four-wave mixing, temporal solitons, and nonlinear effects [17–27,29–32]. However, some limitations that restrict the technological breakthrough have been identified [31]. Following, we review and compare with our proposed devices some relevant works which implement sets of logic gates.

In Ref. [22], it is possible to appreciate all-optical OR, XOR, NOT, XNOR, and NAND logic devices, which are based on the waveguide interference paths approach. The authors reported designs for devices exhibiting a contrast ratio as high as 20 dB under a low power operation regime and a fast response time, lower than 2 ps due to the small footprint area. However, for logic gates up to three inputs, the synchronization and control of the phase difference represent a great challenge. Also, the backpropagation signal to inactive inputs and the unequal threshold values, i.e., the OR and XNOR gates, limit their application to achieve computational circuits. At the same time, the authors proposed the devices under a platform composed of rods of dielectric material in a background medium of air. Unfortunately, these kinds of structures can represent a hard challenge to accomplish their experimental demonstration.

Similarly, in Ref. [26], the authors presented an interesting design for the NOT, AND, OR, XOR, and XNOR logic gates, where the response time is of the order of a few picoseconds (a bit rate of 0.461 Tbit/s) with a low power operation due to their linear regime nature. Nevertheless, the operation of these devices is based on input phase sensitivity, which implies a phase shift to synchronize input signals, increasing the device size. In addition, the power values representing logic 1 and 0 swap for some devices. Indeed, we can observe that Output Logic 0 for their NOT gate is approximately Output Logic 1 for the OR, XOR, XNOR gates. This fact also reflects on a high variance of the device’s contrast ratios. These drawbacks limit their adjacent connection to design circuits and systems.

In Ref. [29] the authors demonstrated, through topological photonic crystal cavities, the OR, AND, NOT, NOR, XOR, XNOR, and NAND logic gates. They remark that the structure designs use a linear interference approach, working with low operating power and demonstrating excellent performance even when a significant amount of disorder exists. In spite of these advantages, the issues with these PhC structures include their input phase dependence and the large footprint area of the PhC structures (up to 100 $\mu$m $\times$ 45 $\mu$m), which lead to a low clock rate.

Interesting and working designs for easily scalable all-optical NOT, AND and NAND logic gates using bandgap solitons in coupled PhC waveguides are reported in Ref. [32]. The authors reported that the logic gates topologies operate with temporal bandgap solitons having stable pulse envelopes during signal processing in the different coupled PhC waveguides. In addition, the building blocks can be cascaded using the output signal from one stage as a new input signal for the subsequent stage aiming at either different logic operators or multiple input logic gate architectures. Equally important, another advantage of this strategy is the absence of intermediate signal amplification between different coupled PhC waveguides stages or even different logic gates due to the soliton nature of the signal pulses. As an example the authors presented the NAND gate built by connecting the proposed AND and NOT gates. Nevertheless, high input power is required, increasing the energy consumption of the devices since additional source signals are necessary. For instance, three signal pulses were applied to achieve the single NOT gate. Also, the coupling between the PhC waveguides realized along the propagation direction within the device could lead to undesired interference effects when disorders or fluctuations are introduced at the holes close to the waveguides. Although authors accomplished a NAND gate by cascading the AND and NOT gates, it still lacks the design of advanced circuits such as the XOR, Half-Adder, or Full-Adder. In addition, it was proposed a bridge section in order to cascade the logic gates. Its design appears to be challenging to achieve for different circuits and could increase the footprint of the devices, decreasing the desired performance. On the other hand, the simulated refractive index used in the PhC structure could be hard to achieve experimentally since it does not correspond to the commonly used materials in Silicon Photonics.

In this work, we presented a complete set of PhC integrated logic gates and circuits with three Levels of Logic Processing (LLP). In this context, we refer to three LLP circuits consisting of three switches connected in a series arrangement, for instance, the FULL-ADDER Sum. On the other hand, the AND, NAND, NOR and FA-Carry are two LLP circuits, while the OR, XOR, FAN-OUT and HALF-ADDER are one LLP. The results of our circuits have shown a CR higher than 5.50 dB, with average of 7.02 dB and confidence interval (CI) from 5.42 dB to 8.61 dB at 95% of confidence level. It demonstrates the small fluctuations of the output, and robustness of our proposed devices. These circuits also exihibit well-defined input and output power values to represent the 1 and 0 logic states, operating at the same input and output wavelength ($\lambda \approx$ 1550 nm). In addition, our integrated circuits are based in the same building block devices without amplification signals between their connections (switches N and P) and have great potential for fabrication since the newest technologies for manufacturing PhC devices allow to obtain devices with an error rate below 5%, with a high rate of repeatability, and at a low production cost [34–38]. We also applied our previously proposed methodology to evaluate the effect of structural disorders on our PhC integrated circuits. Fundamentally, it consists of introducing fluctuations in specific regions in the boundary of the PhC waveguides that form the logic gate structure [25]. The results showed that our circuits can support small phase delay ($\lambda /28$) at the input sources, changes in the input power levels ($\pm 5$ mW), and hole disorder effects around the cavity ($\pm 20$ nm), the most sensitive region. These fluctuations result in about $\pm 5$ mW signal noise at the output for these devices. Table 1 summarizes the advantages of the devices proposed in this paper in comparison with other previously published works.

As a final consideration, we call attention to the development of a PhC cross information device that can help build improved circuits with a smaller footprint area, faster response time, and lower energy consumption. Furthermore, we expect to address a CPCL mathematical model allowing us to enhance the device design process, switching up to a high abstraction level rather than performing large FDTD simulations.

## 5. Conclusion

In this paper, we numerically demonstrated a complete set of PhC integrated circuits with up to two logic processing levels, based on Complementary Photonic Crystal components, including AND, OR, NOR, NAND, XOR, FAN OUT, HALF ADDER, and FULL ADDER logic devices. The proposed systems showed excellent performance for SwN and SwP acting as core hardware devices, where a contrast ratio as high as 5.5 dB was demonstrated. Furthermore, our designs were computationally guided to establish values that reliably represent logic states 1 and 0, guaranteeing an operating wavelength at $\lambda \approx$ 1550 nm for input and output. Last but not least, it is imperative to emphasize that this study also contributes satisfactorily to address improvements for the current telecommunication systems, sensors, and microprocessors chips.

## Funding

Fundação de Amparo à Pesquisa do Estado de Minas Gerais; Conselho Nacional de Desenvolvimento Científico e Tecnológico; Coordenação de Aperfeiçoamento de Pessoal de Nível Superior.

## Disclosures

The authors declare no conflicts of interest.

## Data availability

Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.

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