Monolithic integrated two-stage cascaded SOA-PIN receiver for high-speed optical wireless communication

Yu Lei; Xinda Yan; Chao Li; Erwin Bente; Weiming Yao; Zizheng Cao; Zizheng Cao; Ton Koonen

doi:10.1364/OL.457785

Optics Letters
Vol. 47,
Issue 10,
pp. 2578-2581
(2022)
•https://doi.org/10.1364/OL.457785

Monolithic integrated two-stage cascaded SOA-PIN receiver for high-speed optical wireless communication

Yu Lei, Xinda Yan, Chao Li, Erwin Bente, Weiming Yao, Zizheng Cao, and Ton Koonen

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Yu Lei, Xinda Yan, Chao Li, Erwin Bente, Weiming Yao, Zizheng Cao, and Ton Koonen, "Monolithic integrated two-stage cascaded SOA-PIN receiver for high-speed optical wireless communication," Opt. Lett. 47, 2578-2581 (2022)

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Abstract

Monolithic integrated receivers are highly desired due to the potential of mass production and the reduction of device size and cost. In this Letter, a monolithic integrated optical wireless communication (OWC) receiver with optical preamplifiers is designed, fabricated, and investigated to achieve high sensitivity based on photonic integration technology. The proposed receiver consists of one waveguide PIN photodetector integrated with two semiconductor optical amplifiers (SOAs). Compared with using a one-stage optical amplifier, using two independent SOAs as a two-stage amplifier offers the advantage of optimizing the noise figure of each amplifier independently by tuning their injection currents, which leads to the reduction of the total noise and an improvement of the receiver sensitivity. The achieved sensitivity for a 10-Gb/s OOK signal with 10-dBm launch power at 1550-nm wavelength by using the designed receiver is up to −27.5 dBm at a bit-error-ratio (BER) level of 3.1×10⁻³ over a 0.9-m indoor free-space link. The experimental results show the potential to achieve a high-speed OWC link with high sensitivity by using a cascaded SOA/PIN monolithic integrated receiver.

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Data availability

Data underlying the results presented in this Letter are not publicly available at this time but may be obtained from the authors upon reasonable request.

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Receiver Type	Sensitivity (dBm)	Data Rate/Gb/s	Integration Level
APD-TIA [4]	$- 30$	10	low
PIN-TIA [5]	$- 21$	10	low
PIN-TIA [5]	$- 12.5$	40	low
EDFA-PIN [6]	$- 27.8$	40	low
SOA-PIN [7]	$- 20$	25	low
SOA-PIN-bandpass filter [7]	$- 22$	25	low
SOA-PIN-TIA [8]	$- 25.7$	10	medium
This work	$- 23.8$	10	high

Optical Power/dBm	SOA1+SOA2/mA	SOA1+SOA2/mW	BER
$- 22.5$	47+50	68.2+74.6	1 $\times$ 10 $^{- 13}$
$- 22.5$	41+50.2	56.0+75.0	1 $\times$ 10 $^{- 3}$
$- 24$	46+52	66.1+79.0	4.15 $\times$ 10 $^{- 9}$
$- 24$	43+49.5	59.9+73.5	1 $\times$ 10 $^{- 3}$
$- 25.5$	47+54	68.2+83.6	3.17 $\times$ 10 $^{- 6}$
$- 25.5$	45+50	64.0+74.6	9.75 $\times$ 10 $^{- 4}$
$- 27$	50+53	74.6+81.3	9.22 $\times$ 10 $^{- 4}$

Receiver Type	Sensitivity (dBm)	Data Rate/Gb/s	Integration Level
APD-TIA [4]	$- 30$	10	low
PIN-TIA [5]	$- 21$	10	low
PIN-TIA [5]	$- 12.5$	40	low
EDFA-PIN [6]	$- 27.8$	40	low
SOA-PIN [7]	$- 20$	25	low
SOA-PIN-bandpass filter [7]	$- 22$	25	low
SOA-PIN-TIA [8]	$- 25.7$	10	medium
This work	$- 23.8$	10	high

Optical Power/dBm	SOA1+SOA2/mA	SOA1+SOA2/mW	BER
$- 22.5$	47+50	68.2+74.6	1 $\times$ 10 $^{- 13}$
$- 22.5$	41+50.2	56.0+75.0	1 $\times$ 10 $^{- 3}$
$- 24$	46+52	66.1+79.0	4.15 $\times$ 10 $^{- 9}$
$- 24$	43+49.5	59.9+73.5	1 $\times$ 10 $^{- 3}$
$- 25.5$	47+54	68.2+83.6	3.17 $\times$ 10 $^{- 6}$
$- 25.5$	45+50	64.0+74.6	9.75 $\times$ 10 $^{- 4}$
$- 27$	50+53	74.6+81.3	9.22 $\times$ 10 $^{- 4}$

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Optics Letters