Open Access
Add to BibSonomy
Abstract
Recently infrared photodetectors based on low-dimensional semiconductors have developed rapidly. However, due to its poor light absorption and incompatibility with traditional silicon-based readout circuit processes, the sensitivity and integration of such photodetectors are limited. In this work, we proposes a 64 × 64 quantum dot short-wavelength infrared (SWIR) photodetector composed of carbon nanotube thin film transistor (CNT TFT) and silicon-based ROIC. CNT TFT's gate is constructed by PbS colloidal quantum dots (PbS CQDs) which improve the absorption rate of infrared light. The generated photovoltage is amplified and converted in situ by CNT TFT. Notably, under infrared radiation of 1300 nm, the noise equivalent current reach up to 1.25*10−13A/Hz1/2. At a drain-source bias (Vds)= -0.1 V. The device exhibits detectivity of 5.6*1013 Jones and a fast response of 0.57 ms. The silicon-based ROIC is implemented by CMOS 0.18um process, with a power supply voltage of 1.8 V. It mainly includes a programmable integrator, a sampling and holding circuit, and a 10bit/2.5 MHz successive approximation analog-to-digital converter (SAR ADC). The programmable integrator has four levels of integral gain to meet the application requirements of different infrared light intensities. The experiment results show that the imaging function of the overall photodetector is correct, laying the foundation for the development of carbon-silicon based heterojunction integrated photodetector in the future.
© 2024 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
In recent years, due to the increasing demand for short-wavelength infrared (SWIR) technology in communication, medical, military and other fields, SWIR photodetectors have experienced rapid development. Low-dimensional semiconductors, such as graphene and GaGeTe, have high light absorption rates and excellent process characteristics, making them the construction materials for future infrared photodetectors [1–5]. In order to achieve high-quality imaging, infrared photodetectors also need to integrate readout circuits (ROIC) for signal integration, amplification, and analog-to-digital conversion. At present, the ROIC is still designed and manufactured using mature CMOS process. Because emerging low-dimensional semiconductor materials often require special processing techniques and are not compatible with CMOS readout circuits, the development of SWIR photodetectors is greatly limited.
Carbon nanotube field-effect transistors (CNTFET) have a quasi one-dimensional structure and an ultra long mean free path (MFP), which can achieve extremely high carrier mobility [6–9]. A CNTFET can contain dozens or even hundreds of nanowires as conductive channels, giving it greater current transfer capability [10,11]. In addition, the CNTFET process is compatible with traditional CMOS processes and has the possibility of three-dimensional integration. At the same time, a thick colloidal quantum dot film can be added to the gate of CNTFET technology to increase the infrared light absorption rate. These advantages make CNTFETs a powerful alternative to phototransistors for photodetectors [12–15].
In this work, we demonstrates a SWIR photodetector system, which includes a 64 × 64 carbon-based phototransistor array and a silicon-based ROIC. The gate of carbon-based phototransistors is constructed with PbS colloidal quantum dots (CQDs), so it constructs a CNT thin film transistor (CNTTFT). PbS CQD thin films can effectively absorb infrared light and generate photovoltage at the PN heterojunction of PbS CQD/ZnO thin films. The conductive channel in CNTTFT amplifies the photovoltage in situ and converts it into photocurrent output. The silicon-based ROIC includes an integrator, a sampling and holding circuit (S&H), and a 10 bit/2.5 MHz successive approximation analog-to-digital converter (SAR ADC). A row and column decoding circuit has also been added to the system to gate the 64 × 64 phototransistor array. PbS-CQD CNTTFT and systems were tested separately under 1300 nm wavelength infrared light with a ROIC main clock of 1.5 MHz. The response time of PbS-CQD CNTTFT reaches only 0.57 ms, and the overall imaging effect of the system is good. To the best of our knowledge, this is the first demonstration that PbS-CQD CNTTFT is capable of SWIR detection with fast response speed. Good reproducibility and stability of the measured devices were also observed.
2. Device fabrication
CNTFET can be prepared through two methods: direct CVD growth, solution-based purification and self-assembly. The CVD method has a simple process, making it easy to obtain parallel arranged CNTFET arrays with fewer defects, thus it has been widely adopted. However, the biggest drawback of this method is that it can only achieve one advantage in the high-density, high-purity, or directional arrangement of CNTFET [16–19], and cannot meet the comprehensive requirements of conductive channel applications in CNTFET. Solution-based purification and self-assembly technology is a more effective method for preparing CNTFET. This technology first disperses and separates the original carbon nanotubes grown by arc discharge or CVD method multiple times to obtain semiconductor carbon nanotube solutions with ultra-high purity or even chiral enrichment. Then, self-assembly is carried out to arrange them on the target substrate. Taking all factors into consideration, the CNTFET process in this article is prepared based on solution purification and self-assembly techniques.
Moreover, further optimization can be achieved by using dimensional-constrained self-assembly technology. Firstly, the purified semiconductor carbon nanotubes are attracted from the bulk solution to the dual liquid interface [20]. Afterwards, the carbon nanotubes on the dual liquid interface are slowly transferred to the solid-liquid gas boundary due to wafer pulling and top solvent evaporation convection, and continuously deposited on the wafer surface. By optimizing the liquid phase interface properties, the wafer pulling and solvent evaporation rate, the carbon nanotube concentration in suspension, and the interaction strength between conjugated polymers and the surface of the carbon nanotubes, 100–200 nanotubes/µm with controllable density, an orientation angle deviation less than 8.3°, and a diameter of 1.45 ± 0.23 nm can be prepared. Polycarbazole conjugated polymers is adopted as dispersants. With multiple ultrasonic dispersion, high-speed centrifugation separation, and filtration screening, a semiconductor carbon nanotube solution with a purity of at least 99.9995% is yielded [21]. The prepared dual-gate CNTFET structure is shown in Fig. 1(a), and its SEM image is shown in Fig. 1(b), with a heavily doped substrate as the back gate.
Fig. 1. CNTFET structure and its SEM microphotograph (a) Dual-gate CNTFET structure. (b) SEM microphotograph of Dual-gate CNTFET.
This article applies the CNTFET preparation method discussed above to prepare nanowires (as conductive channels) in CNTTFT. PbS-CQD CNTTFT is a phototransistor composed of low-dimensional semiconductor field-effect transistors (FETs) and CQDs modified on the channel. Due to the excellent light absorption ability and mobility of CQD, PbS-CQD CNTTFT photodetectors have high sensitivity. The PbS CQDs heterojunction on CNTTFT serves as the gate. This device structure achieves effective amplification of optical signals (photovoltage) through capacitive coupling, resulting in high responsiveness. Meanwhile it also enables the photodetector to theoretically have an extremely fast response speed and achieve the best dynamic range (DR) by adjusting the back gate. Figure 2(a) shows the structure of PbS-CQD CNTTFT. Firstly, a single-walled CNT film was deposited on a SiO2/Si substrate, with an average diameter of 1.4 nm. Afterwards, 3 nm yttrium (Y) was deposited onto a CNT film using an electron beam deposition process, and transformed into Y2O3 through thermal oxidation as an isolation layer. To obtain an effective photosensitive structure, it is necessary to sputter 40 nm n-type ZnO onto the Y2O3 dielectric layer between the CNTTFT's source and drain. Further synthesize PbS CQD with a diameter of 3.8 nm through a two-step method. PbS-halide CQD was obtained through ligand exchange in solution in air, and then spin coated onto ZnO to form a 150 nm thick intrinsic CQD film. Finally, the PbS CQD capped with oleate was directly assembled onto the PbS-halide CQD and treated with 1,2-ethyldithiol (EDT) solution to form a 30 nm thick p-type CQD film. The main function of the Y2O3 layer is to partly separate the optical and electrical components, while maintaining strong electrostatic coupling between them to maintain high carrier mobility and low noise performance in CNTTFT. The interface charge of zinc oxide/quantum dots diffuses with each other to form a space charge region, forming an built-in electric field. The electrons drift towards the zinc oxide laye and accumulates, and the accumulated charge is electrostatically controlled by a high-k gate on the CNT. The CNT size is 10um*10um, which has an impact on gate control. However, the control mechanism is relatively complex. Currently, 10um*10um is a suitable size for CNTs. The thickness of the quantum dot absorption layer is 150 nm. If the absorption layer is too thick, it will affect charge accumulation, and if the absorption layer is too thin, it will affect photon absorption efficiency. The photoelectric response process is shown in Fig. 2(b). At a wavelength of 1300 nm, the SWIR photodetector based on PbS-CQD CNTTFT exhibits response rate of 1.65 × 104 A/W, as shown in Fig. 2(c). In Fig. 2(d), the response and recovery time is 0.57 ms and 0.97 ms, respectively. And the detectivity D* of 5.6 × 1013 Jones is demonstrated in Fig. 2(e). The measured noise spectrum is shown in Fig. 2(f).
Fig. 2. Structure and characteristics of PbS CQD CNTTFT (a) PbS-CQD CNTTFT structure. (b) PbS-CQD photoelectric response process. (c) PbS-CQD CNTTFT response rate. (d) response and recovery time of 0.57 and 0.97 ms. (e) the detectivity D* under 1300 nm irradiation at Vds = -0.1 V and Vbg = 0 V in ambient air. (f) the measured noise spectra.
3. Silicon-based ROIC design
Based on the output signal characteristics of 64 × 64 PbS-CQD CNTTFT photoedetector, the design of silicon-based ROIC needs to consider the following aspects: (1) The gain of the integrator circuit (voltage-to-current conversion circuit) needs to be programmable to adapt to the output of different photocurrent amplitude; In this design, the integrating capacitor is programmed using a switch, divided into four levels, to integrate the photocurrent within the range of 1-200 nA to avoid saturation of the output voltage; (2) Considering the response time in milliseconds and detection accuracy requirements, the resolution of the analog-to-digital converter (ADC) needs to reach 10 bits or more. The ADC used in this design adopts a 10 bit/2.5 MHz successive approximation analog-to-digital converter (SAR ADC) structure. Compared with single slope ADCs and Sigma-Delta ADCs, its signal bandwidth is larger, and its power consumption, area, and output signal-to-noise ratio (SNR) performance are relatively balanced [22–25].
The circuit diagram of ROIC is shown in Fig. 3(a). The integrator first converts the output current of the PbS-CQD CNTTFT photoedetector into voltage, and then stabilizes the integration voltage for a period of time through a sampling and holding circuit (S&H). The buffer is used to increase the signal driving ability, and finally, the SAR ADC is used for analog-to-digital conversion. When the flag bit Data_en is valid, standard binary code is output. The bandgap provides current bias for the integrator, buffer, and SAR ADC. The clock generator produces a two-phase non-overlapping clock to ensure the correct operation of the integrator and S&H circuit. The main clock signal is divided by 64 and output to the SAR ADC, allowing the SAR ADC to perform analog-to-digital conversion during the stable stage of the output signal. The basic topology of SAR ADC is shown in Fig. 3(b). In this structure, the first sampling and holding unit samples and holds the analog input signal VIN as an input to the comparator unit. At this point, the binary search algorithm begins by gradually approaching the registers (SAR Logic). Firstly, set the highest bit (MSB) to 1 and all other bits to 0; And add the N-bit code string (100… 0) to the DAC capacitor array. At this time, the DAC outputs an analog voltage of 1/2 VREF, where VREF is the voltage reference gradually approaching the ADC; Then, the analog voltage converted from the DAC is used as the input at the other end of the comparator and compared with the input signal VIN. If the input signal VIN is greater than 1/2VREF, the comparator will output a logic low level, and the highest bit MSB will remain unchanged at 1; If the input signal VIN is less than 1/2VREF, the comparator will output a logic high level, and the highest bit MSB will be set to 0. After determining the highest bit of the codeword, keep the highest bit unchanged, then set the second highest bit to 1 and the other low bits to 0, and add the codeword string to the DAC array to compare the second highest bit of the codeword. Repeat the other low bits one by one until the result of the lowest bit (LSB) is compared, and thus obtain the numerical code corresponding to the input signal VIN.
Fig. 3. Silicon-based ROIC diagram and its timing (a) ROIC structure. (b) SAR ADC structure. (c) Readout timing. (d) Output voltage of integrator.
The operating time of the overall ROIC is shown in Fig. 3(c). In CLK1 phase, the S&H circuit stabilizes the output voltage of the integrator, while performing integrator reset and analog-to-digital conversion to output a binary code; In CLK2 phase, the integrator integrates the current of the PbS-CQD CNTTFT photoedetector. The integrator used in this design is shown in Fig. 3(a), consisting of reset switch S1, integral gain programming switch G1-G4, integral capacitor Cf1-Cf4, and transconductance amplifier. G1-G4 is used to select different integrating capacitors to ensure that the output voltage does not saturate. The reset switch S1 is closed in the clk1 phase and enters the reset state. The OTA input and output are short circuited to eliminate residual charges from the previous operating cycle; in CLK2 phase, the integrator works normally and converts the output current of the PbS-CQD CNTTFT photoedetector into the output voltage. Because the output voltage of the integrator is a ramp signal, for the subsequent analog-to-digital converter to process the signal stably during the conversion cycle, it is necessary to maintain the final output voltage for a period of time. Therefore, the S&H circuit shown in Fig. 3(a) is added. The S&H circuit consists of a CMOS sampling switch and a holding capacitor CH [26–28]. The clock phase of the sampling switch is clk2 that is the reverse signal of clk1, which means that when the integrator is working normally, the output voltage of the integrator charges the holding capacitor CH. When entering the reset phase clk1, the sampling switch is disconnected, and the final value of the integrator output voltage is saved on the holding capacitor CH, whose voltage value stabilizes for half a cycle, making it convenient for ADC to sample and convert. The waveform of the overall integrator and the S&H circuit is shown in Fig. 3(d). The S&H circuit maintains the final output voltage of the integrator at a constant value in clk1 phase.
The DAC of SAR ADC adopts a charge-distribution structure with a single sampling capacitor [29]. And a 10 bit DAC adopts a capacitor distribution of low-level 4 and high-level 6 as shown in Fig. 4(a). When place and route, it is important to minimize the routing of low-level capacitors, minimize the impact of low-level parasitic capacitor on segmented capacitors, and minimize capacitor mismatch. Due to the offset voltage in the comparator, it can cause DC drift in the comparator output, resulting in static errors in SAR ADC. Therefore, the comparator adopts a three-level preamplifier structure with input offset storage and output offset storage [30], effectively reducing the impact of DC offset voltage in the latch and amplifier. The circuit diagram of the comparator and the preamplifier circuit are shown in Fig. 4(b). The ROIC is implemented using 0.18 µm 1P6 M CMOS technology. The power supply voltage is 1.8 V, and the chip microphotograph is shown in Fig. 4(c), with an active area of approximately 1.2mm2. After tapeout, the output signal spectrum of the SAR ADC is shown in Fig. 4(d) when the input signal frequency is 2kHz and the clock frequency is 2.5 MHz. The signal-to-noise distortion ratio (SNDR) is 53.2 dB, with effective number of bit (ENOB) of 8.54bit.
Fig. 4. Silicon-based ROIC chip (a) DAC structure. (b) Comparator circuit. (c) Microphotograph of ROIC. (d) FFT measurement result of ROIC.
4. Experiment results
The overall photodetector consists of 64 × 64 PbS-CQD CNTTFT array, a row and column control circuit board, a ROIC, an FPGA core, and its peripheral circuits. Figures 5(a) - (f) show the system framework diagram, 64 × 64 PbS-CQD CNTTFT array, row and column control circuit board, ROIC, FPGA core and its peripheral circuits, and overall system, respectively.
Fig. 5. The 64 × 64 PbS-CQD CNTTFT photodetector system (a) system framework diagram. (b) 64 × 64 PbS-CQD CNTTFT array. (c) row and column control circuit board. (d) overall system.
In this system, the 64 × 64 PbS-CQD CNTTFT array efficiently converts optical signals to currents. ROIC mainly includes an integrator and an ADC, which are used to receive the current generated by the photodetector array and convert it into digital signal. The Altera Cyclone IV E FPGA serves as the main control core to achieve row and column gating control for the 64 × 64 PbS CQD CNTTFT array, i.e. sequentially conducting each row and column of the photodetector; Simultaneously providing control timing for ROIC and sequentially transmitting the digital signals output by the ROIC to computer, which presents them in the form of images, ultimately achieving the conversion of optical signals to visual images.
Firstly, a separate test is conducted on the ROIC. We use a high-precision digital power supply to provide voltage and measure the relationship between the input current signal Irst and the output digital code. When the power supply voltage is 1.8 V and the clock is 1.5 MHz, the power consumption is 5.16 mW. ROIC can detect photocurrent within a range of 1-150 nA, with a dynamic range of 35.45 dB. The relationship between the input current signal Irst and the output integrated voltage is shown in Fig. 6(a). ROIC can process a maximum current of 300 nA, but has good linearity within the range of 150 nA. Test the output digital code of the ADC with an integral voltage step of 0.1 V. Each voltage generates 4096 digital codes, and the average value of the digital codes is taken to fit the line that coincides with the scatter plot. The linearity is good, reaching 3.67%, as shown in Fig. 6(b). Finally, the dynamic range of the ROIC was tested, and the test results are shown in Fig. 6(c), reaching a maximum of 35.45 dB. The nonlinearity of device response is mainly limited by the integration range of ROIC current. The integral capacitor in a silicon-based ROIC can achieve the conversion of 0-150 nA current to voltage. When the input current exceeds 150 nA, the integral capacitor saturates and linear conversion cannot be achieved, resulting in non-linear response.
Fig. 6. Output characteristics of ROIC (a) The relationship between the input current signal Irst and the output integrated voltage. (b) The relationship between the input voltage signal ADIN of ADC and the integrated voltage output. (c) ROIC dynamic range.
With a wavelength of 1300 nm, the infrared light is irradiated under the PbS-CQD CNTTFT photodetector through the “PKU” and “CNT” mask. The FPGA core controls the ROIC to convert the photoelectric signal generated by the PbS-CQD CNTTFT photodetector into a digital code, and the computer performs grayscale imaging based on the digital code. The final imaging effect is shown in Fig. 7(a) and (b), and the display effect is good. The absorption spectrum of the device has a peak response at 1300 nm. Due to the quantum dot bandgap, the device has a cutoff wavelength of 1400 nm.
Fig. 7. The final imaging effect of PbS-CQD CNTTFT photodetector (a) imaging effect of “PKU” mask. (b) Imaging effect of “ CNT “ mask.
The comparison with similar achievements is shown in Table 1. Due to the application of CNTs, our work has a higher detection rate than other detectors. And the response speed performance is superior.
Table 1. Comparison results
This photodetector, as a three terminal device, adds an additional bottom gate compared to traditional opponents, which can adjust the device to operate in different states through different bottom gate voltages. Controlling the gate voltage can adjust the current between the source and drain, and this adjustment process itself involves power consumption. Based on this adjustment characteristic, the additional bottom gate requires additional power consumption to achieve working state adjustment. The fill factor is an parameter that measures the proportion of the photosensitive area to the entire pixel area. Due to the fact that each pixel must leave space for the connection of three electrodes, the actual area available for photoelectric conversion is relatively reduced, resulting in a decrease in fill factor.
5. Conclusion
In summary, we have fabricated and investigated the optoelectronic properties of a 64 × 64 quantum dot SWIR photodetector consists of PbS-CQD CNTTFT and silicon-based ROIC. The PbS-CQD CNTTFT device exhibited detectivity of 5.6*1013 Jones and a fast response of 0.57 ms under 1300 nm wavelength illumination. Further, the noise equivalent current reach up to 1.25*10−13A/Hz1/2. The performance of silicon-based ROIC is also measured. Under a power supply voltage of 1.8 V, the linearity between the output digital code and the input photocurrent reaches 3.67%, and a maximum photocurrent of 150 nA can be detected with power supply of 5.16 mW. Finally a prototype of 64 × 64 quantum dot SWIR photodetector is constructed. The overall imaging effect is good, which opens up a new direction for the development of new SWIR photodetectors.
Funding
Major Science and Technology Projects of Xiamen (3502Z20221022); Basic and Applied Basic Research Foundation of Guangdong Province (2021B0301030003); Natural Science Foundation of Fujian Province (2023H0052).
Acknowledgment
The authors are thankful to Carbon-based Electronics Research Center of Peking University for the analytical, material characterization, device fabrication, and testing.
Disclosures
The authors declare no conflicts of interest.
Data availability
The data that support the findings of this study are available from the corresponding authors upon reasonable request.
References
1. G. Konstantatos, M. Badioli, L. Gaudreau, et al., “Hybrid graphene-quantum dot phototransistors with ultrahigh gain,” Nat. Nanotechnol. 7(6), 363–368 (2012). [CrossRef]
2. J. Zhang, S.-S. Li, W.-X. Ji, et al., “Two-dimensional GaGeTe film: a promising graphene-like material with tunable band structure and high carrier mobility,” J. Mater. Chem. C 5(34), 8847–8853 (2017). [CrossRef]
3. A. Rogalski, M. Kopytko, and P. Martyniuk, “Two-dimensional infrared and terahertz detectors: Outlook and status,” Appl. Phys. Rev. 6(2), 021316 (2019). [CrossRef]
4. Y. Ding, Z. Cheng, X. Zhu, et al., “Ultra-compact integrated graphene plasmonic photodetector with bandwidth above 110 GHz,” Nanophotonics 9(2), 317–325 (2020). [CrossRef]
5. V. Kucek, C. Drasar, J. Navratil, et al., “Optical and transport properties of GaGeTe single crystals,” J. Cryst. Growth 380, 72–77 (2013). [CrossRef]
6. J. Guo, S. Datta, and M. Lundstrom, “A numerical study of scaling issues for Schottky-Barrier carbon nanotube transistors,” IEEE Trans. Electron Devices 51(2), 172–177 (2004). [CrossRef]
7. J. Zhang, A. Lin, A. N. Patil, et al., “Robust digital VLSI using carbon nanotubes,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 31(4), 453–471 (2012). [CrossRef]
8. G. Brady, A. Way, N. Safron, et al., “Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs,” Sci. Adv. 2(9), e1601240 (2016). [CrossRef]
9. A. Franklin, M. Luisier, S.-J. Han, et al., “Sub-10 nm carbon nanotube transistor,” Nano Lett. 12(2), 758–762 (2012). [CrossRef]
10. C. Qiu, Z. Zhang, M. Xiao, et al., “Scaling carbon nanotube complementary transistors to 5-nm gate lengths,” Science 355(6322), 271–276 (2017). [CrossRef]
11. Z. Yao, C. Kane, and C. Dekker, “High-field electrical transport in single-wall carbon nanotubes,” Phys. Rev. Lett. 84(13), 2941–2944 (2000). [CrossRef]
12. I. Moreels, Y. Justo, B. Geyter, et al., “Size-tunable, bright, and stable PbS quantum dots: a surface chemistry study,” ACS Nano 5(3), 2004–2012 (2011). [CrossRef]
13. X. Qiu, Z. Wang, X. Hou, et al., “Visible-blind short-wavelength infrared photodetector with high responsivity based on hyperdoped silicon,” Photonics Res. 7(3), 351–358 (2019). [CrossRef]
14. H.-S. Kyeong, J. Jaewon, M.-K. In, et al., “Improving of sensitivity of PbS quantum dot based SWIR photodetector using P3HT,” Material 14(6), 1–8 (2021). [CrossRef]
15. S. Zhou, Y. Wang, C. Deng, et al., “Highly sensitive SWIR photodetector using carbon nanotube thin film transistor gated by quantum dots heterojunction,” Appl. Phys. Lett. 120(19), 193103 (2022). [CrossRef]
16. P. Avouris, Z. Chen, and V. Perebeinos, “Carbon-based electronics,” Nat. Nanotechnol. 2(10), 605–615 (2007). [CrossRef]
17. A. Franklin, “Nanomaterials in transistors: From high-performance to thin-film applications,” Science 349, 322–333 (2015). [CrossRef]
18. M. Geier, J. McMorrow, W. Xu, et al., “Solution-processed carbon nanotube thin-film complementary static random access memory,” Nat. Nanotechnol. 10(11), 944–948 (2015). [CrossRef]
19. Q. Cao, S. Han, J. Tersoff, et al., “End-bonded contacts for carbon nanotube transistors with low, size-independent resistance,” Science 350(6256), 68–72 (2015). [CrossRef]
20. Y. Lin, Y. Cao, S. Ding, et al., “Scaling aligned carbon nanotube transistors to a sub-10 nm node,” Science 6(7), 506–515 (2023). [CrossRef]
21. S. Frégonèse, C. Maneux, and T. Zimmer, “A compact model for dual-gate one-dimensional FET: application to carbon-nanotube FETs,” Trans. Electron Devices 58(1), 206–215 (2011). [CrossRef]
22. T. Sun, Y. Lu, and L. Kang, “A buffer direct injection and direct injection readout circuit with mode selection design for infrared focal plane array,” Infrared Phys. Technol. 63, 140–146 (2014). [CrossRef]
23. H. Kulah and T. Akin, “A current mirroring integration based readout circuit for high performance infrared FPA applications,” IEEE Trans. Circuits Syst. II 50(4), 181–186 (2003). [CrossRef]
24. X. Chen and Q. Lv, “A versatile CMOS readout integrated circuit for microbolometric infrared focal plane arrays,” Optik 124(20), 4639–4641 (2013). [CrossRef]
25. J. Johnson and T. Lomheim, “Focal-plane signal and noise model-CTIA ROIC,” IEEE Trans. Electron Devices 56(11), 2506–2515 (2009). [CrossRef]
26. T. Ngo, I. Ukaegbu, M. Kim, et al., “A low-noise image sensor readout circuit with internal timing generator,” IEEE Sens. Lett. 99, 1 (2018). [CrossRef]
27. Y. Chi and H. Lee, “Low-power, high-sensitivity readout integrated circuit with clock-gating, double-edge-triggered flip-flop for mid-wavelength infrared focal-plane arrays,” IEEE Sens. Lett. 99, 1 (2019). [CrossRef]
28. H. Li, A. Hu, Z. Nie, et al., “A 640×512 ROIC with optimized BDI input stage and low power output buffer for CQDs-based infrared image sensor,” Microelectron J. 124, 105435 (2022). [CrossRef]
29. M. Elzakker, E. Tuijl, P. Geraedts, et al., “A 10-bit charge-redistribution ADC consuming 1.9µW at 1 MS/s,” IEEE J. Solid-State Circuits 45(5), 1007–1015 (2010). [CrossRef]
30. A. Shikata, R. Sekimoto, T. Kuroda, et al., “A 0.5 V 1.1 MS/sec 6.3fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits 47(4), 1022–1030 (2012). [CrossRef]
31. E. R. Singh, M. W. Alam, B. Souayeh, et al., “Fast-response ultraviolet photodetector based on Ta2O5 thin film,” Mater Sci: Mater Electron 34, 2228 (2023).
32. B. Moirangthem, M.W. Alam, and N.K. Singh, “Fast switching photodetector based on HfO2 thin film deposited using electron beam evaporation technique,” Appl. Phys. A 129(9), 622 (2023). [CrossRef]
33. A. D. Iacovo, C. Venettacci, L. Colace, et al., “PbS Colloidal Quantum Dot Photodetectors operating in the near infrared,” Sci. Rep. 6, 37913 (2016). [CrossRef]
