Sustainable growth of data-processing bandwidth in high-performance computing requires a substantial reduction of the energy that is consumed for the transmission and detection of every single bit. High-speed optical interconnects offer promising solutions to realize efficient distributed computing architectures, but to date optical links employing pluggable photonic devices still consume tens of pJ per bit, which results in tens of megawatts when scaled up to exascale systems. In order to reduce power consumption in high-speed optoelectronics, connections between the photonic and the electronic hardware have to be shortened as much as possible inside co-packaged devices, and, to this end, CMOS-silicon photonics is envisioned as a key technology, because it enables monolithic integration of photonics and electronics onto the same silicon chip. However making CMOS-silicon photonics work at speed as high as hundreds of Gbps was still a challenge.

In this work, Baher-Jones and coauthors demonstrate the first CMOS-SiPh system, which monolithically integrates all the electrical and optical functionality for an optical transmitter and receiver. The system operates in the O band at a data-rate of 112 Gbps in a PAM4 modulation format and requires an energy consumption as low as 4.3 pJ/bit. The transmitter and receiver chips are fabricated on the same wafer in a 45 nm CMOS technology without any process modifications between the two designs. The authors expect that co-packaging these chips with the required application specific integrated circuits (ASICs) can potentially result in substantial improvements in the energy performance of high-speed computing systems with respect to the use of conventional pluggable optics.

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