1. Introduction

Integrated circuit (IC) designers and manufacturers need to measure the time behavior of electrical signals inside operating circuits for several reasons, including: design validation of new technologies, study of products not performing up to specifications and failure analysis. Presently, such measurements are routinely carried out with two main techniques. The first relies on metal probes that physically contact metal lines to extract electrical signals. The second uses a focused electron beam for probing the time varying electric field along the conducting lines [1]. Innovative testing techniques, as Laser Voltage Probe (LVP) and Thermal Laser Stimulation (TLS), have been recently proposed for debugging high speed integrated circuits. LVP is based on the modulation in intensity induced in an incident laser probe by p-n junction polarization. It is especially suited for studying time-dependent events, since it allows the acquisition of signal waveforms directly from MOSFETs [2]. On its turn, TLS is based on the thermal variation of the conductance of metal lines induced by a focused laser beam; it provides a valuable method for localizing current leakage in ICs [3].

One of the major drawbacks of these techniques is that the electrical signals of interest are measured sequentially. In the case of complex circuits, this results in a prohibitively time-consuming analysis. Moreover, progresses in IC technology have raised further problems [4]: the technical advances obtained in the last quarter of century have exponentially increased the density, complexity and speed of ICs, but also the number of layers within the chip. Dense metal patterns are usually inserted in all areas not populated with signal wires for optimizing chemical-mechanical polishing processes. These metallic layers, often referred to as “back end of line,” have made the signal-carrying metal lines no longer physically accessible to external probes from the front side, without the destructive disassembly of the chip. Alternative techniques, which can remotely sense electrical activity, are actually required for IC testing.

Optical inspection provides a possible answer to this demand, since electrons accelerated by the high electric field at the pinch off region of a field effect transistor (FET) emit bursts of light, which can be collected by a suitable photodetector [5,6]. In fact, these electrons, often referred to as “hot electrons”, can loose the excess energy by emission of photons in the visible and infrared region of the spectrum. The intensity of the light results to depend strongly on both source-to-drain voltage and gate voltage. Theoretical [7] and experimental [8] studies demonstrated that direct transitions of electrons within the conduction band is the main mechanism of photoemission in ICs. In CMOS circuits both n-FETs and p-FETs emit light pulses synchronous with switching events when a sudden current flows in a transistor [7]. Yet, due to lower mobility of holes compared to that of electrons, emission from p-FETs is typically more than one order of magnitude weaker than that from n-FETs produced with the same technology.

Optical inspection can be performed from the front side of the circuit when metallic layers don’t block the emitted photons, but, different from other techniques, it has the great advantage of being applicable from the backside. In this case, since Silicon is opaque to wavelengths shorter than about 1 μm, the emission must be collected with detectors sensitive beyond 1 μm. The substrate of the chip is typically thinned to 50-200 μm to achieve reasonable collection efficiency, without adversely affecting circuit performances.

Two optical techniques have been developed for IC analysis. The first one is known as photon emission microscopy (EMMI) [9] and is based on the time-integrated collection of luminescence from a circuit using a camera with high sensitivity in the near infrared [10]. This technique gives information on the presence of defects in a chip, since failures in ICs often induce a higher emission of light due to increased electron-hole recombination.

The second technique, originally proposed by researchers at IBM, is based on the temporal analysis of photons emitted by CMOS integrated circuits during switching [11]. This method is called picosecond imaging circuit analysis (PICA). It relies on a microchannel plate photomultiplier tube equipped with a spatial resistive anode. Using a multichannel analyzer, the detection events are allocated in a 3D array representing the two spatial coordinates and the time with respect to a reference clock. In this way, it is possible to follow the switching time of various logical ports occurring at different times inside the IC, thus allowing a completely non-invasive testing [12–14].

Moreover, point-like detectors coupled to time-correlated single photon counting (TCSPC) units have been also used for time-resolved circuit analysis. A Single Photon Avalanche Photodiode (SPAD) has been suggested to achieve unpaired temporal resolution and sensitivity. Also infrared detectors like InGaAs avalanche photodiodes and Superconducting Single-Photon Detectors (SSPD) have been proposed [15]. Yet, since all these detectors lack spatial resolution, the measurements must be performed in specific points of interest, previously identified by means of a time-integrated luminescence image [16,17].

In this paper we propose a time-gated image detector for time-resolved circuit analysis. A specific feature of this device is its complete parallelism in the spatial dimensions that makes it suitable to detect simultaneous events, like the switching of the many ports that occurs synchronously in complex ICs (e.g. memories or microprocessors). In practice, a gated intensified camera collects all the photons emitted in the field of view within a very short temporal window [18]. By scanning the delay of the acquisition window with respect to a reference signal, the complete story of emitted photons in the observed area is recovered. State of the art gated-cameras have spatial resolution of more than 100 line pairs and a minimum gate width of 50 ps, thus providing a temporal resolution comparable with the one shown by the best photon counting systems.

To demonstrate the suitability of a similar set-up for circuit analysis, we used a picosecond gated-camera to test a CMOS inverter chain and a static memory provided by STMicroelectronics.

2. Experimental set-up

The experimental set-up is depicted in Fig. 1(a): a time resolved imaging detector, coupled to a metallographic microscope (Leica DM-RE, Wetzlar, Germany), acquires the temporal evolution of the luminescence emitted by the circuit under test, while suitable electronics synchronize the detector with the circuit activity.

The detector is made of a light intensifier (HRI; Kentech, Didcot, UK) based on a 18 mm microchannel plate (MCP) optically coupled to a low-noise CCD camera. The image intensifier provides a nominal acquisition window of 300 ps with an internal jitter of 30 ps. Only photons arriving to the photocathode inside this temporal window are amplified by the MCP and collected by the CCD. The camera (Sensicam, PCO GmbH, Göttingen, Germany) is based on a cooled sensor with 1280 x 1024 pixels and on a 12-bit ADC board. In order to measure the temporal evolution of the luminescence emitted by the device under test, a sequence of images is acquired at different delays. A proper circuit is used to synchronize the intensifier with a signal taken from the device under test; a jitter free delay generator, made of passive cables, provides the delay between the reference signal and the acquisition gate, with a unit step of 25 ps. The whole apparatus is computer controlled by a software written in C language under the LabWindows® environment. The software allows one to set the instrumental parameters and to perform an automatic acquisition of delayed images.

The set-up was characterized in terms of spatial resolution, temporal resolution and sensitivity.

The spatial resolution of the system is limited by the image intensifier: it can resolve 220 line pairs in continuous mode and 150 line pairs in gated mode. The size of the minimum detail that can be resolved depends on the magnification of the microscope lens. The resolution values obtained with a 100X (N.A. 0.75) and a 50X objectives (N.A. 0.55) are listed in Table 1.

Table 1. Spatial resolution of our experimental set-up when using a 50X and a 100X objective.

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The temporal response of the detector was measured using a laser diode (PDL Picoquant, Berlin, Germany) that emits light pulses at λ=650 nm with a Full Width Half Maximum (FWHM) of 100 ps at a repetition rate of 80 MHz. The laser pulses were delivered to the photocathode of the intensifier and a sequence of delayed images was acquired with the nominal time gate set to 300 ps. Figure 1(b) shows the temporal profile of the light intensity measured as a function of the relative delay between laser pulse and gate. The profile is the convolution of the acquisition window with the laser pulse and it results in a FWHM of 380 ps. Assuming, for simplicity, a Gaussian shape for the laser pulse and a rectangular shape for the intensifier gate, the actual gate width results in a value of 360 ps FWHM.

 

Fig. 1. (a) Scheme of the experimental set-up for dynamic circuit analysis; (b): temporal response of the light intensifier convolved with a 100 ps laser pulse.

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The detector sensitivity depends on the spectral response of the photocathode. The S25 surface of our imaging unit provides a usable response (quantum efficiency > 0.5%) up to about 920 nm. Since our detector is blind above 1.1 μm, where the silicon is transparent, we performed experiments only from the front side of the circuits under test. However, photocathode materials with high enough sensitivity in the near infrared are available and could be used for time-resolved imaging from the backside.

The detector shows an extremely low background noise. In a typical acquisition time of 5 min the average background noise is close to 55 counts per effective pixel; the major source of this noise is the ADC board of the CCD, which introduces a read noise of 50 counts per pixel, while the remaining counts are due to the dark noise of both the CCD and the photocathode. Anyhow, both of them can be quite efficiently removed by subtracting a proper background image.

A further source of noise is the shot noise of the amplification unit of the intensifier; in this case, the noise is strictly dependent on the intensity of the signal acquired by the detector and, consequently, it cannot be removed with a simple subtraction. For what concern the acquired images, we estimated a signal-to noise-ratio close to 20.

3. Measurement on an inverter chain

The first test was carried out on a CMOS circuit consisting of a chain of 10,000 NAND ports made with the 0.18 μm technology. The two inputs NAND gates are connected to each other with a grounded input, so they act as simple inverters. A 40 MHz square wave signal delivered to the first gate propagated through the chain. The supply voltage was 3V, instead of 1.8V, which is the nominal value for 0.18 μm technology. The overvoltage was applied in order to increase photon emission and compensate for the low efficiency of our detector in the infrared region.

A preliminary measurement was performed using the intensified camera in CW mode, i.e. without any gate, in order to collect all photons emitted by the switching ports irrespective of timing. The luminescence image was taken with the 50X objective with an integration time of 10 minutes. Figure 2(a) shows the luminescence collected by the detector superimposed on a white light image of the observed portion of the integrated circuit.

 

Fig. 2. (a) Image of the CW luminescence (red spots) emitted by the NAND chain superimposed to a white light picture of the corresponding portion of the circuit; blue arrows indicate the direction of propagation of the electrical signal; (b) profile of the luminescence intensity along a line inside the ellipse.

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Red areas indicate points of photon emission: the electrical signal propagates in a snake manner through the logic ports located along 10 horizontal lines. The signal path is schematically indicated by arrows. Bright columns correspond to metal lines; as expected, they hide some light emitting transistors. Figure 2(b) shows a line profile of the luminescence detected in the region indicated by the dark ellipse in Fig. 2(a): the peaks in the luminescence plot correspond to the switching ports. The spatial resolution of our system is good enough to separate single gates, which appear located at 2 μm from one another.

The intensifier gate width was then set to the nominal value of 300 ps and a sequence of 11 images, delayed by 50 ps from each other, was collected by integrating the photons emitted by the chip for 10 minutes per image. In this case, the measurement was performed using the 100X objective. The electrical signal for temporally synchronizing the intensifier to the CMOS chain was given by the low impedance output of the inverter chain. The jitter between the input square wave and the image intensifier gate was measured with a wideband oscilloscope (LeCroy 9362) and resulted to be less than 50 ps rms.

Figure 3 shows a movie of the acquired images. In each delayed image only small regions of the circuit emit photons, in correspondence with the ports switching during the 300 ps temporal window. The movie shows in a pictorial way the propagation of the signal inside the IC.

 

Fig. 3. (473 KB) Movie showing the time-gated images of the NAND chain; each image is delayed by 50 ps with respect to the previous one.

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The data set provided by our measurements can be analyzed both in the spatial and in the temporal domains. One can consider a single frame of the movie and observe the position of transistors that are switching in a definite time slice. On the other hand, focusing on a point of interest, it is possible to reconstruct the temporal profile of the emitted luminescence. Figure 4(a) and 4(b) provide examples of these kinds of analyses.

Figure 4(a) shows a spatial line profile taken in correspondence of few emitting logic ports at delays 0 ps (black curve) and 50 ps (gray curve). The peaks of the luminescence profiles correspond to the switching NANDs. It is interesting to observe that these peaks appear at a distance of 4 μm, doubled with respect to the actual distance between logic ports. This occurrence indicates that, as expected, only the luminescence from odd NANDs is detected, since these are the ones where the n-FET is switching.

In Fig. 4(b), the temporal profile of the pixels corresponding to 4 logic ports is plotted. The temporal profile results from the convolution between the intensifier gate window and the luminescence pulse emitted by each gate. By calculating the first moment of the temporal emission in each gate it is possible to estimate the propagation delay between odd inverters, which results in about 100 ps.

 

Fig. 4 (a) Line profile of the luminescence emitted by 4 NAND gates; (b) optical waveform measured from the selected gates.

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4. Measurement on a random access memory

A second measurement was performed on a static random access memory (SRAM) made with the 0.18 μm technology. The SRAM architecture is based on a standard 6 transistors cell of 5.9 μm², which is used to build an array of 64 kbits. The access to the memory cells for read or write operation is managed through a synchronous circuitry composed by 3 main blocks: i) decoders, to select the cell in the array; ii) input/output logic, to write and read the data value; iii) control logic, to generate the internal timings that synchronizes properly the operation. A memory access is initiated by the rising edge of the clock; during a read cycle, the data stored in 32 cells of the memory core are selected, detected as digital signals by the sense amplifier and transferred to the output.

 

Fig. 5. Image of the CW luminescence (red spots) emitted by a portion of the SRAM, superimposed on a white light picture of the corresponding portion of the circuit.

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The memory was analyzed during a read cycle, while the clock was running at 25 MHz, driven by a pattern generation board. As already done with the NAND IC, we powered the device to 3 V, instead of the nominal supply voltage (1.8V), to increase the photoluminescence and to speed up the measurement. Figure 5 shows the CW luminescence superimposed on a white light image of the memory. Light emitted by clock, column decoder, precharge circuits, sense amplifiers and output buffers can be recognized as red spots.

For the time-resolved measurements the intensifier gate was set to the nominal value of 300 ps and a sequence of delayed images was acquired with an integration time of 5 minutes per image. In this case, the synchronization between the image intensifier and the SRAM was provided by a buffer circuit, which introduced an extra jitter. The total jitter between the detection system and the RAM resulted in 200 ps rms. Yet, a careful design of the synchronization circuitry should reduce the overall jitter close to the intrinsic jitter of the detection system (less than 50 ps).

Figure 6 is a movie of the luminescence showing the sequence of the operations, as they actually take place during the read cycle. The read cycle begins with the rise of the clock signal that first turns off the precharge circuit in order to let the data lines evolve according to the bit stored in the addressed cells. Data read is performed by enabling the sense amplifier that latches the data to the output buffer. Finally, all signals go back to the initial state, ready for next reading: precharge turns on, address lines are deselected and sense amplifier is disabled.

 

Fig. 6. (1284 KB) Movie showing the time-gated images of the SRAM analyzed during a read cycle.

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As already mentioned, the main feature that differentiates our imaging set-up from existing ones is the parallel acquisition of photons all over the observed field. This aspect allows one to easily check for the simultaneity of events that take place far apart from each other. Figure 7 shows a plot of the luminescence emitted as a function of time by points along a line across the sense amplifier circuitry. The occurrence of luminescence peaks in the same time frame corresponds to the synchronous switching of the sense amplifiers, as expected in a well behaving circuit.

 

Fig. 7. Plot of the luminescence emitted by 7 sense amplifiers in the SRAM, as a function of time. The horizontal line indicates that the switching events are synchronous.

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The time occurring between the rising edge of the clock and the availability of data in the output lines is called access time. Typical access time for random reading at 25°C and 1.8V is about 2.7 ns. From our measurements the access time turned out to be 1.5 ns. This discrepancy is due to the higher supply voltage (3V) applied during luminescence measurements. In fact the extra voltage is expected to speed up the electrical signal inside the IC, since a higher current is available to charge the device capacitances.

5. Discussion and conclusions

In this paper we proposed a different approach to PICA based on a time-gated parallel detector. The luminescence emitted by the circuit is sliced in many time-delayed frames by the gated intensifier.

Important features come from this approach. System operation is certainly simpler than in case of a photon counting apparatus. Moreover, it offers intrinsic spatial parallelism and do not suffer from any limitation imposed by the simultaneous emission of photons from many sites inside the IC, as typically observed in complex devices, like microprocessors or random access memories.

A further valuable advantage of using a gated camera is the multi-modality operation. In fact, with the same detector, without any moving part and using a single microscope port, three image types of the portion of the circuit under test can be taken: i) a white light image, obtained at low gain with a short acquisition time to get the circuit layout; ii) a time-integrated luminescence image, acquired at high gain to record the luminescence intensity in the field of view; iii) a series of time sliced images to recover the timing inside the circuit. Gated and white light images can be combined for an easy interpretation of the luminescence, without any scaling factors or misalignment which might affect image superimposition when different detectors are used.

The analysis of the complete evolution of the signals inside an IC for a clock period is really time consuming and it might take several hours. Yet, in many cases, the project validation of an IC or its failure analysis involve the check for specific signal patterns, which might require the acquisition of only few gated images at very specific delays. In this case our set-up would be very appropriate and the IC inspection would require only few tens of minutes.

Nevertheless, it is important to underline that the proposed apparatus suffers from some drawbacks, which limit its use in the present implementation. However, these drawbacks could be overcome with some hardware improvements. In particular, the spectral sensitivity of the photocathode represents a severe limitation for the analysis of ICs from the backside. Yet, infrared sensitive photocathodes do really exist and a proper time-gated infrared camera could be assembled by a couple of manufacturers if the marketing perspectives justified the development effort.

Further, the light intensifier used for the present study has a measured gate width of about 360 ps, which might seem inadequate for IC testing. Nevertheless, the internal jitter of our detection apparatus is close to 50 ps. Hence, if enough photons can be accumulated in each time slice, differential images of two adjacent gates can be calculated to improve the time resolution.

As a final remark, a further improvement of this approach to PICA could consist in the integration of the gated camera with a photon counting single-pixel system, based, for example, on a SPAD. The single-pixel detector, in fact, thanks to its superior temporal resolution and high sensitivity, could provide a further refinement of the luminescence time plots in critical points of the IC.