1. Introduction

Laser diodes intimately integrated within silicon integrated circuits (ICs) have long been sought for a wide range of optical interconnect applications and for a variety of sensor needs. For the most part this need is being met currently by flip-chip bonding vertical cavity surface emitting laser (VCSEL) arrays on top of individual integrated circuit die, often followed by removal of the array substrate [1]. While this technique has been widely used, it none the less has important limitations including non-planarity of the final assembly resulting in incompatibility with bump bond packaging and three dimensional integration, increased thermal resistance of the surface-mounted VCSELs, limited density with which devices can be integrated and the restriction that they be arranged in an array, decreased yield because devices are processed in multiple VCSEL units, and incompatibility with full 200 and 300 mm diameter wafer scale processing.

In the mid-1990’s several groups briefly explored integrating VCSELs on silicon in the form of individual device pills, but none of the efforts was pursued to the point of achieving full integration of VCSELs on an IC. Daryanani, et al, fabricated 100 µm diameter mesa VCSELs, freed them from their substrates, and soldered them on Al pads on top of a Si IC chip [2]. The top contacts on the bonded lasers were not connected directly to the underlying circuit, but were instead contacted by an external probe tip. About the same time, Tu, et al used ion etching to produce VCSELs in the shape of truncated pyramids and assembled them in matching recesses made in the surface of a silicon wafer with an anisotropic etchant [3]. In this case both contacts on the VCSEL were brought out to pads on the silicon surface, but there was no circuitry on the Si, i.e. it was not an IC chip.

We report application of a new heterogeneous integration technique we call Recess Mounting with Monolithic Metallization (RM³) Integration [4] to fully integrate VCSELs with CMOS integrated circuits. Individual VCSEL device pills like that shown in Fig. 1, were bonded on contact pads revealed at the bottom of recesses etched into the dielectric stack covering a custom designed commercially processed Si integrated circuit chip and interconnected with the underlying circuitry through etched vias and patterned thin film metal lines similar to those used in the IC itself. When driven by on-chip Si transistors the VCSELs show threshold currents and thermal characteristics similar to those of native substrate devices.

 

Fig. 1. A scanning electron micrograph of a completed VCSEL pill mounted for viewing purposes with indium on a flat silicon substrate. The VCSEL diameter is 35 µm at the top and 55 µm at the bottom, and the height is 8 µm. (The material surrounding the pill is not present in recess-mounted devices.)

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2. Fabrication and integration

Fabrication of the micro-scale standalone VCSEL device pills was similar to standard VCSEL processing, with steps added to remove the devices from their substrate and to pattern contact and bonding layers on their bottom surface. The process began with a commercially grown VCSEL epitaxial wafer from a wafer foundry [5]. A standard three quantum well Al_xGa_1-xAs top-emitting 850 nm VCSEL structure, modified by adding a 0.5 µm thick InGaP etch-stop/ selective-etch layer immediately after the initial buffer layer on the substrate, was used; no other changes were made to the heterostructure design. The Al_xGa_1-xAs heterostructure was etched into an extensive fairly dense array of tall cylindrical mesas extending down to the etch-stop layer using a sulfuric wet etch [6] with a PECVD SiO₂ mask. The mesa tops were 35µm in diameter, while the side profile of the mesas sloped out to a bottom mesa diameter of 55µm. An oxide current aperture, with a 10µm diameter opening, was then formed in the structure [7]. P-type top contact rings (6.5, 50, 50, and 130 nm of Pt, Ti, Pt, and Au, respectively) were e-beam deposited on the planar top surfaces of the mesas, and patterned using lift-off.

With the pill top surface processing completed, processing continued with substrate removal, followed by deposition and patterning of the n-side contact and bonding metals. The array of VCSEL mesas was first temporarily bonded face down to a silicon handle wafer using the commercial embedding polymer, WaferBond^TM [8]. The GaAs substrate is selectively etched away to the InGaP etch stop layer using a sulfuric acid/hydrogen peroxide wet etch [6]. The InGaP was selec-tively etched away at this stage exposing the WaferBond^TM and the n-type GaAs bottom contact layer of the embedded VCSELs. Photoresist was spun on this surface, and patterned using contact photolithography. A sequence of n-type contact metals (5, 10, 50, 90, 30, and 180 nm of Ni, Au, Ge, Au, Sn, and Au, respectively) was deposited and lift-off patterned.

With backside processing completed, the pills are released from the WaferBond^™ by immersing the sample in the remover. (A typical pill is shown in Fig. 1.) The released pills are collected, rinsed, and stored in isopropyl alcohol (IPA) until needed. Several dozen pills were dispersed on a metalized microscope slide prior to assembly and probed to sort them by threshold and cull defective pills. It was found that the yield of functioning pills was high (estimated to be above 90%) and that the range of continuous wave (CW) threshold curent was from 1 to 2.5 mA. This variation is traceable to variations in pill diameter introduced when the mesas were wet etched and can be corrected by using a dry mesa etch.

The IC chips onto which the VCSEL pills were integrated had been designed by Travis Simpkins [9] in a 0.5 µm 3-metal CMOS process and obtained from MOSIS [10]. The chip had a number of 100 µm square pads (VCSEL landing sites) formed in the lowest metal level, M1, and connected to the drains of n-channel MOS drive transistors with gates 100 µm wide and 0.6 µm long. The threshold voltage of these transistors is 0.8 V, and the K-factor is approximately 10 mA/V²; their sources were connected to the chip ground bus. Adjacent to each M1 landing site there was a 10 µm by 100 µm contact pad for making connection to the top (p-side) of the VCSEL; it was formed in the top metal layer, M3, and connected to the chip power supply bus. The ground and supply buses on the chip and the individual gates of each of the drive transistors could be accessed from bonding pads around the perimeter of the IC chip.

Recesses for assembly were prepared by etching a 75 µm diameter round hole through the 3 µm of dielectric covering the M1 pad [11]. After opening the recess to the M1 landing pad, a sequence of metals (5, 180, 640, and 210 nm of Cr, Au, Sn, and Au, respectively) was deposited and patterned on the aluminum pad. The Au and Sn layers form the AuSn eutectic bond [12] to the Au layer on the n-type side of the pill.

For assembly, individual device pills were picked up using a quartz micropipette vacuum pick up tool [13]. Using the micropipette, the pills were aligned and placed into their recesses one at a time until all of the recesses were filled. The VCSEL pills were then solder-bonded permanently in place by heating the assembly to 315^° C in a forming gas ambient and under a conformal 40 PSI bonding pressure, provided by a pressurized thermal polymer, to form the AuSn eutectic metallic bond. A 3×3 array of VCSEL devices within recesses on an IC chip is shown in Fig. 2; at this point the devices can be probed to confirm that they are satisfactorily bonded and still operational.

 

Fig. 2. A photomicrograph of a 3 by 3 array of VCSEL pills bonded in recesses on a CMOS chip prior to BCB replanarization, contact via formation, and interconnect metal deposition and patterning. The VCSELs can be tested at this stage to confirm good back-side contact and bonding.

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After bonding a 1.5µm thick layer of benzocyclobutene (BCB) [14] was spun on the IC chip and cured, after which a 1µm layer of silicon dioxide was also deposited on the chip. Together these dielectric layers encapsulate the VCSELs and re-planarize the chip. Contact vias were etched through the dielectrics to the contact pads on the IC and pills, metal was e-beam deposited over the surface, and the p-side interconnects patterned. (The n-side contact was connected to the circuitry during the VCSEL bonding step.) A fully integrated device is shown in Fig. 3.

 

Fig. 3. A photomicrograph of a VCSEL pill fully recess integrated within a CMOS chip. The metal pattern seen connects the top contact ring of the VCSEL to the CMOS drive circuit below it on the IC chip.

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3. Device characteristics

VCSEL pill devices bonded onto IC recesses and tested by probing their top contact exhibited CW threshold currents ranging from 1 mA to 2.5 mA based on L-I measurements, showing that no degradation occurred during assembly and bonding. The optical output of the bonded VCSELs rolls off between 15 and 20 mA, indicating that a good thermal heat sink was obtained with the bond.

Fully integrated devices could also be probed directly because the chips were not encapsulated, and their L-I characteristics were similar to those VCSELs on their native substrates. For integrated VCSELs driven via the on-chip electronics, the equivalent of an L-I measurement is a measurement of the light output as a function of the MOSFET gate voltage when the chip is activated (i.e., with power and ground buses biased at 5 and 0 V, respectively). Figure 4 shows the CW light intensity for an integrated VCSEL (I_th=2.5 mA) as a function of the gate voltage of its drive transistor.

The thermal impedances of VCSEL pills bonded in recesses on ICs and similarly processed VCSELs still on their original substrates were compared to assess the impact of integration on this important parameter. The shift of the lasing wavelength with increasing drive power dissipation in the device [13] was measured and converted to a thermal impedance using separate measurements of the VCSEL emission at a fixed drive level as a function of the ambient temperature. It was observed that devices on their original substrates showed temperature increases as low as 2.1 C^°/mW, and VCSELs bonded in recesses on an IC showed increases as low as 1.5 C^°/mW. A typical range of values was from 2.0 to 3.0C^°/mW, and 1.5 to 2.5 C^°/mW, respectively. These results are consistent with Gauss-Seidel iterative thermal modeling results that will be reported separately [15].

 

Fig. 4. The CW L-V_GS and I-V_GS curves for a VCSEL RM³-integrated on a Si-CMOS chip and controlled via the gate voltage on an n-channel drive transistor.

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4. Conclusions

The pseudo-monolithic micro-scale hybrid integration technique used in this work to integrate small diameter, low threshold Ga_1-xAl_xAs VCSEL pills intimately within the dielectric stack of a commercially fabricated Si IC can equally well be used to integrate devices fabricated from any semiconductor with state-of-the-art silicon electronics, enabling unique integrated systems. The integration was done after all conventional Si IC processing has been completed meaning the technique is highly modular and compatible with fabless manufacture; recess mounting of the devices insures that the final assemblies can be highly planar and compatible with flip-chip, solder bump packaging and 3-D integration.

Standard manual pick-and-place assembly was used in this work, albeit with uniquely small micro-pipette vacuum pick-up tools, but the device pills fabricated can also be used in more parallel assembly techniques such as fluidic self-assembly [3] and magnetically assisted statistical assembly [16]. Standard processing techniques were used to fabricate the device pills from heterostructure wafers produced in a wafer foundry and by using a dry etched mesa the device variation observed will be reduced.