1. Introduction

All-optical buffer memories are desirable as key elements of all-optical packet-switched networks that address the contention and congestion of optical packets with high-operation data rates and low-power consumption. Optical buffer memories consisting of flip-flop devices [1–4] have a great advantage compared to those of the fiber-loop type [5]: the data stored in the flip-flop memories can be read out at arbitrary timings, while the buffering time of the fiber loop is limited to multiples of the fiber delay time. We previously proposed an optical buffer memory with shift register function consisting of a two-dimensional (2-D) array of polarization bistable vertical-cavity surface-emitting lasers (VCSELs) [1]. Each polarization bistable VCSEL in the 2-D array acts as a 1-bit flip-flop memory with small optical input power and dc power consumption. In addition, the 2-D array can be monolithically integrated into a small area and potentially contributes to downsizing of the overall memory. We have demonstrated that buffer memory using four InAlGaAs/InP VCSELs can store and regenerate 4 bits of 500-Mb/s data signals in a 1550-nm range [6].

The achievable highest data rate of each 1-bit VCSEL memory is one of the most important performances. The fastest 1-bit buffering achieved so far has been for 10-Gb/s return-to-zero (RZ) signals using an InGaAs/GaAs VCSEL in a 980-nm range [7]. Buffering of signals faster than 10 Gb/s has not yet been achieved, partly because the operating conditions become quite limited when the data rate is increased.

In this paper, we report 1-bit memory operation for both 20-Gb/s RZ signals and 40-Gb/s non-return-to-zero (NRZ) signals using a 980-nm polarization bistable VCSEL. First, the conditions of the peak power and frequency detuning of the data signals required for the 20-Gb/s memory operation are characterized. Then, we describe our successful memorization of an arbitrary bit of a pseudorandom bit sequence (PRBS) data signal of up to 2⁶-1 bits at 20-Gb/s. We have also achieved memorization of each bit of 6-bit NRZ signals at 40 Gb/s. These are the fastest operations of optical bistable flip-flop memories to the best of our knowledge.

2. Principle

A polarization bistable VCSEL has a square mesa structure and two lasing modes with polarization directions orthogonal to each other (0° and 90°). The polarization state of the polarization bistable VCSEL output light is stable because one of those two modes suppresses the other mode through cross-gain saturation. When a control light with sufficient power and the polarization direction parallel to that of the suppressed mode is injected into the polarization bistable VCSEL, the power balance between the two modes is inverted and the lasing polarization state of the polarization bistable VCSEL is switched as shown in Fig. 1 . The AND gate and 1-bit memory functions are achieved as follows (Fig. 2 ). The 90° (0°) polarization state of the polarization bistable VCSEL is used to store “0” (“1”) of the target bit in the data signal. Initially the polarization state is preset to 90° by injecting a reset pulse. Then a data signal with a 0° polarization direction is injected into the polarization bistable VCSEL. The injection power of the data signal is set to less than the polarization-switching threshold of the VCSEL. A set pulse with a 0° polarization direction is also injected. If the set pulse is injected simultaneously with a “1” data signal and the combined injection power of the data and set pulses exceeds the polarization-switching threshold, the polarization state of the VCSEL switches from 90° to 0°. Therefore, the polarization state of the VCSEL reflects the “0/1” of the target bit in the data signal. A polarizer placed after the VCSEL converts the polarization switching of the output light into on/off switching. The stored “0” or “1” of the target bit can be read out using an optical gate device at any timing until the polarization state is reset to 90°.

 

Fig. 1 Polarization bistable operation of VCSEL by injection of optical pulses.

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Fig. 2 1-bit buffering using polarization bistable VCSEL. (a) Implementation and (b) timing chart.

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3. Device description and experimental setup

Our 980-nm VCSEL consists of a three-quantum well In_0.18Ga_0.82As/GaAs active layer, 27 pairs of n-doped DBR layers on the output side, and 38 pairs of p-doped DBR layers. The cross section of the square mesa is 6 × 6 μm² [8]. Figure 3(a) shows polarization resolved light output versus current (L-I) curves. Lasing in 0° polarization direction started from 3.5 mA. Higher output power compared to Ref [8]. was due to the reduced DBR layers on the output side. The lasing was hindered under certain bias conditions from the interference between the reflection of the DBR layers and the reflection at the output facet. Figure 3(b) shows the hysteresis of the polarization resolved output. When we increased the current from the non-lasing region around 9.0 mA, lasing in 90° polarization direction started abruptly at around 9.27 mA (1). When we decreased the current after the lasing, the lasing was kept until around 9.10 mA (2’). When we increased the current instead, the lasing polarization switched to 0° direction at around 9.29 mA (2). Then the lasing in 0° polarization direction switched back to the lasing in 90° polarization direction when we decreased the current to around 9.17 mA (3). Thus polarization bistability was obtained at around 9.17 to 9.29 mA. The lasing wavelength of the VCSEL when operated in the polarization bistable region was around 982 nm.

 

Fig. 3 Polarization resolved L-I curves of VCSEL. (a) Overview and (b) magnified views around bistable region.

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Figure 4 shows the experimental setup for the ultrafast memory operation. In this setup, 20-Gb/s RZ or 40-Gb/s NRZ electrical signals were generated from a 4-ch pulse pattern generator (PPG) combined with a 40-Gb/s electrical time domain multiplexer (ETDM MUX). Due to the channel limitations of the PPG and the MUX, the optical data signals and optical set pulses were generated by the same tunable external cavity laser diode (EC-LD) and the same LiNbO₃ modulator. Three set pulses and three groups of data signals were consecutively generated by the modulator. The output of the modulator was divided into two parts by a 3-dB fiber coupler, and one part was delayed using a delay fiber so that the timing of the set pulses matched that of the data signals. The data signals and set pulses were combined through another 3-dB coupler. The polarization directions of both the data signals and set pulses were set to 0° using polarization controllers (PCs). The relative phase between the data signals and set pulses was set to be in-phase by a phase shifter with a proportional-integral-derivative (PID) controller. The in-phase condition was obtained by minimizing the optical power at the branch port of the 3-dB coupler. The data signals and set pulses should be generated from different laser sources in the realistic situation. In this case, coherent combing of two different laser lights should be achieved. In principle this coherent combing should be possible using optical phase lock loops [9]. Incoherent combining of the data signals and set pulses may be another option. The reset pulses were generated using another EC-LD and LiNbO₃ modulator, and they were inserted before and after each data signal group. The polarization direction of the reset pulses was adjusted to 90° using a PC. The width of the reset pulse was set to 300 ps, and only small detuning was applied in the 20-Gb/s RZ operation because the reset operation does not require fast switching. In the 40-Gb/s NRZ operation, we could not use any output port of the 4-ch PPG for generating a reset pulse because all the output ports of the PPG were occupied by the ETDM MUX. Reset pulses of 100-ps width were generated by electrical signals from an ETDM demultiplexer instead, which demultiplexed the 40-Gb/s electrical signals from the second output port of the ETDM MUX. The input signal to the VCSEL was monitored using a 30-GHz sampling oscilloscope, while the VCSEL output waveform through an inline polarizer was monitored using a 20-GHz PIN photodiode and a 13-GHz digital storage oscilloscope. The output light of the VCSEL was collimated by an antireflection (AR)-coated objective lens and coupled into a single mode fiber with an AR-coated angled facet through another objective lens. The temperature of the VCSEL was stabilized to 20.0°C using a thermoelectric controller. The maximum peak power of the data signals measured between these two objective lenses was 250 μW, which was limited by the maximum output power of the EC-LD. The maximum peak power of the set pulses measured between the objective lenses was 190 μW; this was slightly lower than the maximum data signal power because of the insertion loss of the phase shifter and the connection losses of the delay fiber.

 

Fig. 4 Experimental setup. EC-LD: external cavity laser diode, ETDM MUX: electrical time domain multiplexer, ETDM DEMUX: electrical time domain demultiplexer, LN: LiNbO₃ modulator, OSA: optical spectrum analyzer, PBC: polarization beam combiner, PC: polarization controller, PD: photodiode, and 1, 3, 10 dB: optical coupler.

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We used two methods to measure the frequency detuning between the input and output signals of the VCSEL. One method measures the beat signal between the two optical signals. The other measures the optical spectra of the two signals using an optical spectrum analyzer (OSA). The beat signal method had higher accuracy compared to the method using the OSA and was used for detailed analysis of the polarization switching, which will be explained in section 4.1. It was difficult, however, to quickly measure the beat signal while maintaining the conditions to obtain the highest optical input power to the VCSEL. Therefore, the OSA was used to quickly measure the detuning in the case of a memory operation, which will be described in sections 4.2 and 4.3.

4. High-bit-rate memory operation

4.1 Operating conditions of memory

As the data rate of the memory operation is increased, the temporal width of each 1-bit data signal and set pulse needs to be shortened. Higher injection power is then needed for the shortened pulses to obtain polarization switching. When the bit length of the data signal becomes long, change in the number of carriers in the active region of the VCSEL, caused by each data signal, accumulates and causes undesired polarization switching even without set-pulse injection. One solution for this problem is to detune the carrier frequency of the data signal f _data from the oscillation frequency of the VCSEL, f ₀ [7]. Larger frequency detuning Δf ( = f _data - f ₀) requires higher data signal power P _data for polarization switching to occur [10]. Therefore, it is important to grasp the conditions for correct memory operation in the Δf - P _data relation.

We characterized conditions for the memory operation of 20-Gb/s, 2⁶-1-bit PRBS RZ data signals. The details of the characterization will be described in another paper. As explained in section 3, the beat method was used to precisely measure the frequency detuning between the set pulses and the VCSEL output light. Figure 5(a) shows the measured operating conditions. We also studied the operating conditions by numerical simulation, and the results are shown in Fig. 5(b). We only investigated the frequency detuning of Δf < 0 in the experiment because the numerical simulation suggested that the operating conditions would appear only when the detuning value was negative. The solid lines in both figures show the minimum data power necessary to cause polarization switching by in-phase injection of a 25-ps 1-bit “1” data signal and a 25-ps set pulse. The power of the set pulse and the data signal was assumed to be the same. The wavelength tolerance of the input optical pulse was wider on the longer wavelength side [10]. The dotted lines show the minimum switching power by a 1-bit “1” data signal without a set pulse. The dashed lines show the switching thresholds by a long-bit data signal (2⁶-1-bit, PRBS) without a set pulse. When the data signal power is set below the solid line, polarization switching does not occur even if a 1-bit “1” data signal and the set pulse are injected simultaneously. Thus, a “1” data signal cannot be memorized. When the data signal power is set above the dashed line, on the other hand, successive injection of the 2⁶-1-bit PRBS data signal will cause undesired polarization switching without set-pulse injection. When the data signal power is set above the dotted line, a 1-bit “1” data signal will cause undesired polarization switching. Therefore, the solid line indicates the lower limit of injection power and the dashed line indicates the upper limit of injection power for proper operation. We regarded the shaded regions surrounded by the two limit curves to be the operating conditions. The upper limit curve (dashed line) of Fig. 5(b) had several dips caused by a relaxation oscillation of about 6-GHz frequency and the sidebands of the input data signal ( ± 20 GHz). Therefore, to prevent undesired switching caused by the 20-Gb/s long-bit data signal, we should set the frequency detuning Δf < −24 GHz.

 

Fig. 5 Operating conditions for 20-Gb/s PRBS RZ data input. (a) Measurement and (b) numerical estimation.

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4.2 Memory operation for 20-Gb/s PRBS RZ signals

We performed 1-bit memory operation for 20-Gb/s PRBS RZ data signals. The bias current was set to about 9.28 mA in the bistable region where we obtained polarization bistability (Fig. 3(b)). The output power of the VCSEL was about 430 μW. As we explained in section 3, the OSA was used to measure the wavelength detuning. The lasing wavelength of the VCSEL was about 982.43 nm with the 0° polarization state. The wavelengths of the data signals and the set pulses were set to about 982.50 nm. The wavelength detuning of the data signal against the lasing wavelength of the 0° polarization mode was about + 74 pm, which corresponds to Δf = −22.9 GHz. The accuracy of the wavelength (frequency) detuning measured using the OSA was estimated to be about ± 2 pm ( ± 0.6 GHz) from the calibration using the beat method. This measurement accuracy was sufficient for the predicted operating conditions shown in Fig. 5. The maximum optical powers obtained in this experimental setup were used for the input data signals and set pulses as described before (250 and 190 μW, respectively). These wavelength detuning and power of the data and set pulses were about the same as the operating conditions shown in Fig. 5(a). The wavelength of the reset pulses was set to about 982.48 nm, and the lasing wavelength of the 90° polarization mode of the VCSEL was about 982.47 nm. The wavelength detuning of the reset pulses against the lasing wavelength of the 90° polarization mode was about + 13 pm (~-4.0 GHz). The peak power of the reset pulses was set to 55 μW. This all-optical memory operation had an optical gain even for such a high data rate: i.e., the VCSEL output power (430 μW) was higher than the data signal power (250 μW).

Figure 6 shows the results of the memory operation for 2⁶-1-bit PRBS data signals. For the data signals in the three successive groups (1)–(3), three set pulses were positioned to sample “0”, “0”, and “1” data at the beginning of each group (left part of Fig. 6(b)). The 0° polarization component of the VCSEL output is shown in the left part of Fig. 6(c). The signal-to-noise ratio was impaired by large losses of the fiber connections and low responsivity of the InGaAs-based high-speed photodiode for the 980-nm signal. When the “0” data signal and the set pulse were injected simultaneously (i.e., only the set pulse was injected), the 0° polarization component of the VCSEL output slightly increased during the injection, but complete switching did not occur. When the “1” data signal and the set pulse were injected simultaneously, complete polarization switching from the 90° state to 0° state was triggered by the injection of the set pulse. The polarization state of the VCSEL returned to 90° by injection of the reset pulse. The middle and right parts of Fig. 6 show the results when the timing of the set pulses was changed. By only changing the timing of the set pulses without changing the power and the wavelength, we have successfully demonstrated sampling of the three bits (“0”, “1”, and “1”) in the midst of each group (middle part of Fig. 6(c)) and the three bits (“1”, “0”, and “1”) at the end of the 2⁶-1-bit PRBS data signals (right part of Fig. 6(c)). These results show the ability of the current polarization bistable VCSEL memory to handle RZ data signals of 20 Gb/s.

 

Fig. 6 Memory operation for 20-Gb/s, 2⁶-1-bit PRBS RZ data signals. (a) Magnified data signal without set pulses (top) and VCSEL input with set pulses (bottom), (b) VCSEL input, and (c) VCSEL output (0° polarization component).

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4.3 Memory operation for 40-Gb/s NRZ signals

We also examined memory operation for 40-Gb/s NRZ signals. The bias current was set to the bistable region (about 8.82 mA), which was slightly shifted from the region shown in Fig. 3(b) after the 20-Gb/s measurement due to long-term operations. Higher input optical power was required for polarization switching under this bias condition than that required under the condition described in sections 4.1 and 4.2. Because of the limitations of the input optical power (250 μW for the data signals and 190 μW for the set pulses), the wavelength detuning of the data signals and the set pulses against the VCSEL output light was limited to about + 63 pm (Δf ~-19.6 GHz). As explained in section 3, we had to reduce the width of the reset pulses from 300 to 100 ps because we had to use the ETDM DEMUX instead of the PPG to generate the pulses. Therefore the reset pulse power was increased to 210 μW to compensate for the reduction of the reset pulse width.

Measured waveforms of 6-bit 40-Gb/s NRZ data signals are shown in Fig. 7(a) . The data waveform with a “011101” pattern is shown in the left part. The waveform is also shown in the right part by dashed lines. The solid lines in the right part show the waveforms of the data signals with set pulses positioned in each bit slot. The pulse tails of each “1” data in the NRZ data signals caused problems. For example, when the set pulses were positioned to the “0” data bits as shown in (1) and (5) in the figure, they interfered with the pulse tails of the adjacent “1” data bits and were significantly intensified. Consequently, the difference in the combined optical power of the sampled bit and the set pulse became indistinct for “0” or “1” sampled bits. Despite this difficulty, memorization of each bit of the 6-bit NRZ signals was achieved by injecting six groups of 6-bit NRZ data signals with properly-positioned six set pulses and reset pulses into the VCSEL. The input and output waveforms of the memory are shown in Figs. 7(b) and 7(c). The wavelength of the data signals and the set pulses was set to about 982.42 nm. The lasing wavelength of the VCSEL was about 982.36 nm for the 0° polarization state. When the “0” data signal and the set pulse were injected simultaneously, polarization switching of the VCSEL did not occur. In contrast, when the “1” data signal and the set pulse were injected simultaneously, the polarization state of the VCSEL switched from 90° to 0°. The output power of the VCSEL was about 320 μW, and this memory operation also had an optical gain. Unfortunately, however, 40-Gb/s memory operation with a 2⁶-1 bit length has not been achieved yet, partly because of the interference problem mentioned above and partly because of the input power limit of our experimental setup. We expect that shortening the set pulse width and increasing the input data signal power will be effective for solving these problems. In combination with the reduction of the Q factor of the VCSEL, we are on the way to achieving all-optical memory operation for long-bit data signals at 40 Gb/s.

 

Fig. 7 Memory operation for 6-bit 40-Gb/s NRZ data signals. (a) Magnified data signal without set pulses (left part, and dashed lines in right part) and VCSEL input with set pulses (solid lines in right part), (b) VCSEL input, and (c) VCSEL output (0° polarization component).

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5. Conclusion

We demonstrated all-optical 1-bit memory operation for 20-Gb/s PRBS RZ signals and 40-Gb/s NRZ signals using a polarization bistable VCSEL in a 980-nm range for the first time. A 1-bit data signal was arbitrarily sampled and memorized from the 2⁶-1-bit 20-Gb/s data signals and 6-bit 40-Gb/s data signals by changing only the timing of the set pulses. These are the fastest operations of optical bistable flip-flop memories to the best of our knowledge. Results in the present paper show the high potential of all-optical flip-flop memories based on polarization bistable VCSELs for use in ultrafast all-optical future networks.