1. Introduction

Microprocessors are moving from a multi-core to a many-core architecture. There is a bottle neck for electrical interconnects between cores: copper interconnects have a maximum bandwidth of about 10GB/s. To meet the inter-core communication needs of the new architecture, bandwidths of 200GB/s to 1TB/s are needed. Optical interconnects offer an alternative and promise much higher bandwidths. However, in order to serve as inter-core interconnects, they need to be easily fabricated and have low loss/cross-talk [1].

Silicon-on-insulator (SOI) rib waveguides have been studied extensively and are a potential choice for on-chip optical interconnects [2, 3]. Very low propagation losses have been achieved [4], where side wall roughness limits the propagation length of these types of modes [5,6]. However, since rib waveguides support transmission of both TE and TM polarization, great care must be taken to minimize the birefringence in both the group and phase velocity of operating waveguides [7]. Also, for electronic purposes, SIMOX (separation by implantation of oxygen) wafers are favorable over bonded SOI wafers, partially due to the thin buried oxide (BOX) layer in SIMOX materials. Rib waveguides suffer radiative losses through the thin BOX layer in SIMOX wafers, and therefore are less compatible with SIMOX wafers [8].

Surface plasmon (SP) based waveguides offer an alternative to rib waveguides. It is well known that SP supporting structures allow for very tight confinement of SP modes, some structures having confinement well below the SP wavelength. Exploitation of these properties could greatly improve the compactness of optical devices and open up new possibilities in the commercial use of optical signals, particularly at telecommunications wavelengths.

However, designing SP modes which can propagate sufficiently far for inter-core (or even cross-chip) interconnects is problematic due to ohmic losses [9–11]. To mitigate this, many designs of plasmonic waveguides, including insulator-metal-insulator and metal-insulator-metal geometries [12, 13], different surface shapes such as V- and W-structures [14–16], SOI and other slab waveguide coupled plasmons [17–19], and various other structures [20–25], have been proposed and studied. Sub-wavelength dielectric layers that have an index higher or lower than the index of the bulk material have been placed adjacent to metal in various waveguides to extend the propagation length of the modes or improve confinement [18,26–32]. Many of these latter waveguides have been dubbed hybrid plasmonic/dielectric waveguides.

Here, we study such a hybrid plasmonic/dielectric waveguide structure fabricated on an SOI wafer. The waveguide is extremely easy to fabricate using only VLSI compatible methods. Small adjustments to waveguide parameters, easily performed using VLSI compatible methods on the same waveguide, can change the waveguide propagation properties (confinement, effective index, and propagation length). On bonded SOI wafers with thick buried oxide, the effective index can be made to continuously pass through the silicon index, without passing through any cut-off. Because the light line defines the dispersion relation of a plane wave traveling in a medium with an effective propagation index of the index of the material, this means that the dispersion relation of the waveguide can be made to pass through the silicon light line. When the effective index is below the silicon index, the optical power is concentrated in the device silicon away from the metal, and very long propagation lengths are achieved. When the effective index is above the silicon index, tight (sub-micron) confinement suitable for on-chip optical elements is achieved, and the waveguide is compatible with SIMOX wafers.

2. Methods

All 2-D profile simulations were calculated using a commercial finite element package, Comsol Multiphysics. For slab structures (1-D profiles), mode profiles and propagation characteristics were solved with a transfer matrix mode solver. All simulations were performed at 1550 nm free space wavelength, which falls in the telecommunications C band. Technologically relevant oxides for silicon electronics (SiO₂ and various high-k replacements) have indices of refraction ranging roughly from 1.5 to 2. Unless otherwise stated, we chose to use a central device oxide index of 1.8. Silver is typically used for testing of plasmonic structures because it has low metallic losses. For the sake of comparison, unless otherwise stated, simulations assumed silver metal with an index of 0.148 + 11.57 i at 1550 nm wavelength [33]. The silicon and buried oxide indices of refraction used in simulations were 3.48 and 1.5, respectively. The use of CMOS compatible metals, different oxides, and varying geometric parameters are also discussed.

Hybrid plasmonic waveguides were fabricated on diced 1 cm square pieces of bonded silicon-on-insulator (SOI) wafers. Two wafers were used, one with a 3 μm device layer and 4 μm buried oxide (BOX) layer, and the other with a 4 μm device layer and 4 μm BOX layer. Thermal oxide was grown on the two wafers in a dry oxidation furnace. Following this, 5 μm wide aluminum lines were patterned across the full length of each 1 cm square using conventional optical lithography and liftoff of 80 nm thick evaporated aluminum metal. The end facets were polished to minimize insertion losses and artifacts introduced by scattering at the facets.

Measurements were taken on the fabricated waveguides using the apparatus in Fig. 5(a). The light source was a fiber coupled laser operating at 1550 nm wavelength. The output fiber was coupled into a fiber based polarization controller (Thorlabs FPC560) and then end-fire coupled into one facet of the waveguide. The output from the other facet was imaged using a Vidicon camera with a long working distance NIR microscope objective.

3. Waveguide structure

The waveguide structure, shown in Fig. 1(a), consists of an SOI wafer with a device silicon layer of thickness t_d and buried oxide thickness t_b. It is covered by a thin device oxide layer of thickness t_o, and a metal strip of thickness t_m that is on the order of 100 nm thick (this is rather unimportant as long as the metallic nature of the strip is unaffected by being too thin [34]). The strip width, w_m, is nano- to micro-scale. The oxide layer need not cover the whole surface; it can be limited to the region below the metal strip and the waveguide will still function, but here we present results where the oxide covers the entire surface. Note that the waveguide naturally forms an MOS capacitor, which has been used with rib waveguides to create electro-optic modulators via free carrier index modulation [35]. The fabrication of this structure is compatible with VLSI processing methods, the only processing steps necessary being growth or deposition of a thin dielectric layer (SiO₂, SiN_x, etc.) and deposition of a metal line.

 

Fig. 1 Waveguide Geometry and Simulated Mode: (a) schematic of the basic waveguide structure (layer thicknesses not to scale); and (b) finite element simulation of the magnetic field (H-field) showing the modal profile for 1550 nm excitation. The pseudo color scale in (b) represents the magnitude of the magnetic field, while the arrows are a snap-shot of the vector magnetic field. For the simulation in (b), the thickness of the oxide, t_o = 10 nm, the width of the metal strip, w_m = 2 μm, the thickness of the metal strip, t_m = 80 nm, the thickness of the device silicon layer, t_d = 2 μm, and the thickness of the buried oxide layer, t_b = 4 μm. (c) and (d) show images of fabricated structures: (c) shows an overhead view of metal lines fabricated via lift-off, and (d) shows polished end-facets of an 1 cm² SOI chip.

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Figure 1(b) shows an example mode profile for such a structure. One issue that arises when discussing profiles of different waveguides is what field should be discussed. Figure 2 shows several visualizations of the mode profile of Fig. 1(b). It shows the four most commonly discussed (and likely most important) fields. One interesting effect is that due to the boundary condition on the perpendicular component of the electric field, there is a discontinuity of the perpendicular electric field proportional to the ratio of the indices of refraction. This only applies to the perpendicular component of the electric field and thus TM modes. The Poynting vector is proportional to the transverse electric field, so it is also discontinuous by the same ratio. The time averaged energy density also shows a discontinuity, although not by exactly the same ratio as for the perpendicular electric field.

 

Fig. 2 Different Field Visualizations: Different field profiles with insets showing line cuts for the structure in figure 1(a) showing how different fields are discontinuous or continuous at the silicon-oxide boundary: (a) magnetic field, both magnitude and vector field; (b) electric field, both magnitude and vector field; (c) time averaged Poynting vector (power flow directed into the page); (d) time averaged energy density.

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This field enhancement in low index regions is the principle behind dielectric slot waveguides [36, 37] and has been used as a method of field confinement for various plasmonic waveguides and devices as well [32, 38]. When incorporated with very high index materials such as silicon, very high electric fields can be attained in a thin, low index region adjacent to the silicon as illustrated in Fig. 2. However, when the low index layer is very thin (a few nm, which is typical for these waveguides and devices), the majority of the integrated intensity is still predominantly outside the low index region, and the effective index of the modes and hence the decay of the fields in surrounding regions is only slightly changed. This is important when visualizing the field and for many figures of merit as they involve the area in which some field is greater than 1/e of its maximum value, which will be discussed in Section 5. The introduction of a thin low index layer in many waveguides will dramatically increase some figures of merit, while only slightly changing the confinement and propagation characteristics of the mode. Therefore, care must be taken when comparing waveguides with very thin low index layers if the field used in the figure of merit is the electric field, Poynting vector, or average energy density. Because the magnetic field does not suffer from this confusion, it is used for the majority of discussion in this paper and used as the field in all figures of merit.

This structure only supports modes with the magnetic field parallel to the device layer (TM), as can be seen in Fig. 1(b) and for practical purposes, the modes can be considered pure TM modes. There is a small deviation from parallel very near the edge of the metal line. In the case of Fig. 1(b), the integral of |H_y|² in the silicon is 0.037% of the integral of |H_x| ². For narrower metal strips, the deviation can be more pronounced although the mode remains predominantly TM. In addition, the overlap (and hence coupling) of the mode with a symmetric TE polarized beam will be negligible, since any deviation of H⃗, from horizontal is asymmetric: to left of center, H⃗, points down, and to the right, H⃗, points up.

To understand the polarization selectivity of the modes, it is useful to consider 1-D slab waveguide modes (infinite transverse metal line width). Modes for both polarizations in the layer structure of Fig. 1(a) with and without the metal (Fig. 3) were examined. For TE polarization, introducing the metal reduces the mode index by roughly -0.02%. [Fig. 3(c)]. In contrast, for TM polarization, the metal increases the mode index by about +0.3% [Fig. 3(b) and Fig. 3(d)]. The boundary condition at the metal surface effectively repels TE radiation and attracts TM radiation; this behavior can be seen clearly in the simulations of Fig. 3.

 

Fig. 3 Slab Waveguide Modes: Mode profiles (magnitude of E-field or H-field) for different slab (1-D) structures: (left) TE E-field and TM H-field modes for structure without the top metal layer; (right) TE E-field and TM H-field modes for structure covered completely by top metal layer. The thicknesses of the rest of the layers are the same as in Fig. 1(a). The horizontal lines in the mode profiles indicate the locations of boundaries between the device silicon and device oxide (upper line) or buried oxide (lower line) layers. Note the field in the red circles for the TE modes, which show how the field is pushed away from the metal surface, slightly decreasing the effective index. For TM polarization, the field is more dramatically attracted toward the metal.

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Demonstrations that a metallic layer can perturb TE and TM modes of a dielectric waveguide have been previously reported [39–41]. For certain geometric parameters and sufficiently long waveguides, the TM mode is essentially removed due to its greater interaction with the metal and higher ohmic losses while the TE mode survives. In the present case, the increased effective mode index for the TM mode allows for transverse confinement when the metal is confined to a strip; the negative Δn for TE radiation is actually anti-guiding, so the TE light diffracts laterally out of the waveguide. Therefore, the polarization selectivity of the waveguide considered in this paper originates from confinement discrimination rather than attenuation. We also note that one could make a waveguide by coating the entire top surface with a metal film with the exception of an uncoated linear region that would define the waveguide. This would guide TE radiation but not TM. Due to this polarization selectivity, these waveguides could have applications as on-chip polarizers.

As mentioned in the introduction, the tradeoff between losses and confinement in plasmonic waveguides is an important consideration. Because no etching processes are required to confine the waveguide mode, no surface roughness is introduced by etching, and losses due to surface roughness are minimized relative, for example, to a rib waveguide design. Metallic losses are still present for the TM mode in Fig. 1(b) and must be controlled. This is accomplished by adjusting the characteristics of the device oxide layer in conjunction with the metal line width. Optically, the purpose of the device oxide is to decouple the mode from the metal in a controlled manner. This decoupling has a number of important effects. It can cause the majority of the field strength to move into the silicon device layer reducing the interaction with the metal surface and ohmic losses (imaginary part of the effective index). It also controls how much the real part of the effective index under the metal is changed and hence controls the mode profile. For weakly perturbed configurations, the effect of the metal is analogous to that of the dielectric strip in dielectric strip loaded waveguides where the strip is placed on a slab waveguide to slightly increase the effective index below the strip and create guided modes [42,43]. There are important differences, however, in these approaches. A dielectric strip, for example, increases the index of both TE and TM modes hence both polarizations are guided. In addition, as will be discussed next, sub-micron scale confinement can be achieved using the hybrid plasmon/dielectric waveguide approach, which is not possible using dielectric strip loaded waveguides.

One interesting property of the hybrid plasmon/dielectric waveguide is that the effective mode index can cross through the silicon index, or in other words, the dispersion relation can cross through the silicon light line. Figure 4 shows this effect for the slab structure of Fig. 3 (with the metal) as the oxide thickness is changed. This can also be achieved for the 2-D profile structure of Fig. 1(a) (see below). Note that for low oxide thicknesses, the field is evanescent in the silicon (curvature is positive), and for larger oxide thicknesses, the field is radiative in the silicon (curvature is negative). Right at the crossing point, the field profile has no curvature. For the lower oxide thicknesses up to the crossing point these waveguides are compatible with SIMOX wafers, as they are non-radiative in silicon, and hence will not radiate through the thin BOX layer.

 

Fig. 4 Moving Through the Light Line: Mode profiles for the slab waveguide structure as the thickness of a high-k oxide (n=2) is changed. The other thicknesses are the same as in Fig. 3. The inlaid graph shows the real part of the effective index of the modes and the decay constant (alpha) as a function of oxide thickness.

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4. Experimental verification

Hybrid plasmonic devices were fabricated and tested as shown in Fig. 5. Figure 5(b) shows the simulated mode profiles (Poynting Vector) for TM polarization for the two waveguide geometries. For TE polarization the simulations show no guided modes as discussed above. Figure 5(c) and 5(d) show images of the emission for both polarizations for the waveguides. The observation of emission from the device silicon layer in Fig. 5(c) clearly confirms the presence of a guided mode for TM polarization. The absence of the mode for TE polarization supports the plasmonic nature of the waveguide. The two measured profiles show the same trend as the simulation, matching relatively well to the simulated profiles. The simulations show significantly tighter confinement. We attribute this to the limited resolution of the measurement system. The manufacturer quoted resolution of the objective was 1.1 μm, and because the free space wavelength is 1.55 μm, we are very near the fundamental resolution limit. The fact that it is a resolution issue is partially confirmed by the fact that there is signicant field observed above and below the device silicon, where no matter the guiding scheme, the field would be expected to be zero. Therefore, considering the resolution issues, we believe these results match very well. This confirms the presence of the modes, validating the simulation results.

 

Fig. 5 Experimental Verification: (a) Schematic of experimental setup used to image waveguide profiles. Two waveguides were measured and simulated in (b)-(e): (left) t_d = 2μm, t_o = 13 nm, n_o = 1.5, t_m = 80 nm, w_m = 5μm; and (right) t_d= 3μm, t_o = 24 nm, n_o = 1.5, t_m = 80 nm, w_m = 5μm. (b) Simulations and (c) measured TM profiles for the two waveguide structures; (d) Measured TE profiles (no guiding observed) for the two waveguide structures.

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5. Control of propagation and confinement

The propagation loss of a waveguide is defined in terms of the loss in power typically measured in dB per centimeter. This can be related to the imaginary part of the effective index, n_i:

where e is the base for the natural logarithm, λ₀ is the free space wavelength, P₀ is the incident power, and P is the power after propagating by a distance z. An alternative measure of the propagation loss is the propagation length, L, defined as the distance it takes for the power in the mode to decrease by 1/e:

where α is the decay constant of the waveguide defined as 2πn_i/λ ₀. Ref. [44] presents different loss related figures of merit for waveguides with 2-dimensional profiles. We use $M_1^{2D}$ from that paper as a figure of merit for our waveguide defined as

where A_e is the area enclosed by the 1/e field magnitude contour (here, we use the magnetic field for the reasons discussed above). For the parameters of Fig. 1(b), the propagation loss was calculated to be 53.1dB/cm, L = 0.82 mm, and $M_1^{2D}=1243$ . As seen from the simulation, the peak field strength is in fact located well away from the metal, which explains the long propagation length.

The plasmonic interaction in the structure, and hence the mode profile and propagation length, can be controlled by changing the width of the metal strip and/or the thickness of the device oxide. Also, if the metal line width is kept sufficiently narrow for a set device oxide thickness, only a single mode is guided. Higher order modes can be achieved by increasing the metal line width if they are desired (not shown here). An example of controlling confinement/propagation losses by changing the metal line width is shown in Fig. 6(a)–6(d). Note the first two profiles both have sub-micron confinement while the propagation lengths are, in fact, fairly long, reaching 0.16 mm for Fig. 6(b). Similar ratios of confinement to propagation length have been acheived for surface plasmons in air [45]; however, these ratios are much more difficult to acheive in silicon where the high index of silicon results in higher plasmonic losses for a given confinement. As seen from Fig. 6, the propagation length can be increased to many millimeters keeping micron scale confinement. Figure 6(e)–6(h) illustrates how the plasmonic interaction of the mode and the metal can be controlled by changing the oxide thickness. The metal strip width particularly can easily be varied at different locations on the same chip or even along the length of a single waveguide, this structure allows considerable flexibility in on-chip waveguide design.

 

Fig. 6 Controling Mode Characteristics: Mode profiles (magnitude of H-field) for different metal line widths and oxide thicknesses: (a) t_o = 3 nm and w_m = 500 nm; (b) t_o = 3 nm and w_m = 400 nm; (c) t_o = 3 nm and w_m = 300 nm; (d) t_o = 3 nm and w_m = 250 nm; (e) t_o = 3 nm and w_m = 500 nm; (b) t_o = 4 nm and w_m = 500 nm; (c) t_o = 5 nm and w_m = 500 nm; and (d) t_o = 6 nm and and w_m = 500 nm. The thickness of the device silicon is t_d = 2μm, the thickness of the device oxide is t_o = 3 nm and the thickness of the metal is 80 nm for all simulations. The single contour that is shown bounds the region where the H-field is greater than 1/e of its peak value. The H-field vector is predominantly horizontal (TM) in all images. The figures of merit, $M_1^{2D}$ , and the propagation lengths are also shown.

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Various device oxide indices were also studied. Increasing the device oxide index of refraction for fixed thickness has essentially the same effect as decreasing the thickness of the device oxide at fixed index. This is because when there is less index contrast between the silicon and the device oxide, the oxide is less effective at shielding the mode from the metal, and hence has the same effect as a decrease in oxide thickness.

Notably, these modes may be tuned for extremely long propagation lengths maintaining reasonable oxide thicknesses and metal line widths. For example, the simulated propagation lengths for the fabricated structures in Fig. 5 are 1.07 cm and 34.2 cm for t_o = 13 nm, t_d = 3μm and t_o = 24 nm, t_d = 4μm, respectively. The figures of merit ( $M_1^{2D}$ ) for these waveguides are 7,095 and 86,240, respectively. This is using aluminum as the metal, showing proof of concept for very long range modes with CMOS compatible metals and fabrication.

For a direct comparison between different metals, aluminum, copper and silver were all simulated for different waveguides. The results showed that changing the metal left the mode profile (and confinement) relatively unchanged, while the propagation length varied with the conductivity of the metal. For example, changing the metal in a longer range structure (w_m = 4μm, t ₀ = 20 nm, t_d = 2μm) from silver to aluminum (n=1.44 + 16.0 i) changed the propagation length from 7.0mm to 2.2mm; changing it to copper (n=0.757+10.4 i) yielded a propagation length of 0.90mm.

Also, the profiles in Fig. 5 are much more symmetric than typical silicon-compatible plasmonic mode profiles. Symmetric plasmonic mode profiles have been acheived using a small nano-scale wire surrounded by a dielectric or placed between two dielectric layers with low index contrast [45]. However, the large index contrast of silicon, and the diffulty of embedding a nanowire into a silicon wafer makes this method not feasible for silicon-compatible applications. By making a waveguide with a more symmetric mode profile near input or output facets, insertion losses can be decreased when coupling directly to and from optical fibers, which have symmetric modes. Once coupled into the hybrid waveguide, the metal line width or oxide thickness can be changed continuously to modify the mode profile for use on chip. The control of the mode profile through the metal line width has potential for mode conversion devices or couplers between fibers/rib waveguides and plasmonic waveguides/devices.

6. Discussion

A hybrid plasmon/dielectric waveguide in SOI wafers has been predicted through simulations and demonstrated experimentally. Simulations predict propagation lengths (>30 cm) that are sufficient for cross-chip or inter-core interconnects. For optical processing or for regions of the chip that require a higher density of optical elements, configurations of this waveguide can exhibit sub-micron confinement with greater than 100 μm propagation lengths. The waveguide can continuously change from a long range mode to a tightly confined mode (or vise versa) by simply changing the metal line width (or the device oxide thickness/index) along the waveguide. This could particularly be useful for low insertion loss mode conversion between optical fibers or rib waveguides and plasmonic optical components. In addition, the waveguide is single polarization, eliminating concerns associated with birefringence, and can be made single mode for sufficiently narrow metal line widths (all structures presented here are single mode). The basic waveguide structure is compatible with VLSI fabrication techniques and naturally forms an MOS capacitor that may be used for active device integration. The dispersion relation of these waveguides can pass through the light line for silicon. For configurations of the waveguide where the effective mode index is above the index of silicon, the waveguide is compatible with SIMOX wafers. These properties make this an interesting novel structure for integration of optical components on a silicon chip and inter-core interconnects.