1. Introduction

Optical packet switching (OPS) is a promising solution for future flexible networks with low latency, low power, and high bandwidth utilization [1,2]. The realization of an OPS router requires the forwarding functions of label processing, switching, and buffering for high-speed asynchronous burst optical packets. By means of effective use of both optics and electronics, we have constructed a prototype hybrid optoelectronic router that performs the above functions with reduced power and latency [3,4]. The router is implemented by combining key optical/optoelectronic device/sub-system technologies and complementary metal–oxide–semiconductor (CMOS) electronics in a novel router structure.

In a packet-switched network, multi-hop transmission is an essential requirement, and one of the key ways to reduce power and latency is to increase the transparency of the nodes, where electrical buffering/processing of the packets is minimized. A critical issue is thus how to overcome the signal quality degradation of the packets when they transparently traverse multiple optical nodes in the network. Optical 3R regeneration techniques may solve this problem. However, providing a regenerator at every port for each wavelength-demultiplexed channel at each node excessively increases power consumption, size, and cost. Moreover, even with 3R regeneration, coding overhead for forward error correction (FEC) would be necessary because an extremely low bit error rate (BER) is required for intermediate links in order to guarantee reliable end-to-end transmission without FEC at the destination node (e.g., a BER <10⁻¹⁴ is required for each link to achieve a BER <10⁻¹² after 100 hops). This requires high-quality components, such as low noise amplifiers and highly isolated filters as well as high launched optical power, which hinders the realization of low-power networks at low cost.

Considering these issues, we have previously proposed a multi-hop transmission scheme as an alternative, in which 3R regeneration and FEC are selectively performed in an optoelectronic shared buffer every N hops, with the number of hops monitored via the time-to-live (TTL) field in each packet label, as shown in Fig. 1 [2]. The CMOS-based optoelectronic buffer can easily perform not only 3R regeneration but also FEC when needed at a network node. This further relaxes the BER requirements for the intermediate links and thus enables as transparent network as possible with minimized electrical buffering at the nodes. We have so far demonstrated error-free (BER <10⁻⁹) multi-hop (four hops) operation using the hybrid optoelectronic router without buffering [5]. In this paper, we demonstrate multi-hop operation by means of the proposed TTL-based selective error correction function, which is implemented at the shared buffer of the prototype hybrid optoelectronic router. Degraded packets with BER <10⁻³ due to multiple hops are successfully restored by the buffer. This can greatly expand the number of hops while keeping the BER low.

 

Fig. 1 Hybrid optoelectronic router architecture (left) and multi-hop transmission scheme in OPS network (right). The packet is forwarded to the shared buffer (red line, left) every N hops for 3R regeneration and FEC. TTL: time-to-live. AWG: arrayed waveguide grating. SPC: serial-to-parallel converter. PSC: parallel-to-serial converter.

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2. Multi-hop transmission scheme with hybrid optoelectronic router

When an optical packet traverses multiple optical nodes without 3R regeneration (right, Fig. 1), the packet signal quality gradually degrades because it suffers from some unwanted effects, such as the addition of ASE noise from optical amplifiers, band-limitation of optical/electrical components (filter effect), and pulse broadening due to dispersion in fibers. In order to resolve these issues, in our scheme, an initial TTL value of mN-1 (m: integer) is attached to the TTL-field of each packet at the edge node. At the core nodes, with the TTL-field monitored and decremented by the label processor, the packet is sent to the shared buffer for 3R regeneration and FEC once the TTL value indicates that a multiple of N hops (TTL mod N = 0) has been traversed. This is done before the FEC limit (BER <~10⁻³) is reached.

Figure 1 (left) illustrates the architecture of the hybrid optoelectronic router which acts as the core node. The packet data is organized into wavelength layers (four vertically overlayed planes in the figure), separated and combined with AWGs at the inputs and outputs, respectively. Each incoming packet passes through a label processor to update the label (swap address, decrement value of TTL-field). The label processor is followed by an optical switch. If there is no contention caused by other incoming packets, the packet is routed through the switch to the desired output port and passes through the router transparently (i.e., no buffering). Buffering of the entire packet is done only in specified instances when there is a need to resolve contention or to perform various functions (3R and FEC, for Quality of Service (QoS) and multicast, etc.).

Figure 2(a) shows the configuration of the label processors and a 6x6 optical switch connected to the shared buffer (one overlayed plane in Fig. 1, left). Inside the label processor [LP, Fig. 2(b)], the label of the input packet is first separated from the payload by a 1x2 switch (SW), driven by an electrical clock-pulse generator (ECG) [2]. The separated label is fed into a PD. The PD’s output electrical signal is then sampled in parallel [serial-to-parallel converter (SPC)] by an optically clocked transistor array (OCTA) optoelectronic integrated circuit (OEIC). The input label itself is used as a trigger for the OCTA, which enables the conversion of asynchronous optical label. The label is then written into the CMOS scheduler, which determines and generates a new label for the packet and control signals for the optical switch according to a forwarding table. Here, the TTL value of the label is decremented by 1 to indicate the single hop experienced. The new label is fed back into the OCTA in parallel and converted to a serial signal [parallel-to-serial converter (PSC)]. A delayed version of the input optical label is used as the PSC trigger. After E/O conversion, the new label is coupled to the payload to produce the label-swapped packet, which is fed to the switch. The processor swaps only the label while keeping the payload in the optical domain. In this way, payload buffering is avoided, resulting in a reduction of power consumption and latency. The OCTA enables a compact, low-power label processor for high-speed burst optical packets [6].

 

Fig. 2 Diagrams of (a) the shared buffer connected to the label processor and switch (one overlayed plane in Fig. 1, left), (b) a single label processor, (c) a 6 × 6 switch, and (d) a shared buffer. (e) Photograph of the prototype hybrid optoelectronic router. ECG: electrical clock-pulse generator. TWC: tunable wavelength converter. FWC: fixed wavelength converter. APD-TIA: avalanche photodiode and transimpedance amplifier. LN: lithium niobate. OCPTG: optical clock pulse-train generator.

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The non-blocking, wavelength-routing switch [Fig. 2(c)] employs a double-ring-resonator coupled tunable laser diode (DRR TLD) and an NxN cyclic AWG. Inside the switch, the label-swapped packet first enters a tunable wavelength converter (TWC) consisting of a burst-mode receiver front end [avalanche photodiode and transimpedance amplifier (APD-TIA)], a drive amp, a lithium niobate (LN) modulator, and the DRR TLD. Control signals from the scheduler tune the TLD wavelength for the desired path across the AWG. The packet data is then encoded onto the TLD output, which is received by a fixed wavelength converter (FWC) consisting of the same APD-TIA front-end, drive amp, and an electro-absorption modulator integrated distributed feedback laser (EA-DFB) to convert the signal wavelength back to the original input wavelength. The DRR TLD enables a fast (less than 10-ns switching time), stable (<5-GHz wavelength drift), and low-power optical switch [7].

At a multiple of N hops, the packet is forwarded to the shared buffer [Fig. 2(d)]. In the buffer, the high-speed input packet is first converted to slow parallel signals by an all-optical SPC controlled by optical clock pulses generated from an optical clock pulse-train generator (OCPTG). The SPC uses a semiconductor surface-normal all-optical switch operating by means of a differential spin-excitation method to provide a high on/off ratio (> 40 dB) and tunable operation speed (10 Gbit/s to 1 Tbit/s) [2]. The OCPTG consists of an optical clock-pulse generator (OCG) and a fiber-loop based pulse-train generator (PTG). The OCG generates a single synchronized optical pulse per incoming preamble-free asynchronous optical packet and the PTG converts the single pulse to an optical pulse train. The pulse train has a precise repetition rate (the same as the line rate divided by the number of SPC/PSC channels) and duration matching the input packet length [8]. After O/E conversion, the parallelized packet data is then written into CMOS, where the data is stored until the desired output port becomes available. Here, FEC, such as Reed-Solomon (RS), is also performed on the packet data by the CMOS. For readout, the data from the CMOS enters an OCTA-based PSC in parallel. The PSC converts the parallel signals to a serial signal when triggered by another OCPTG driven by the packet envelope electrical signal from the CMOS. After E/O conversion, the error-corrected, 3R-regenerated optical packet is retrieved, which is routed to the output port via the switch. The SPC, PSC, and OCPTG modules fabricated for this prototype can transform 10-Gb/s burst optical signals into successive 16-parallel electrical signals at 625 Mb/s and vice versa. The burst-mode compliant interface devices enable buffering/processing of high-speed asynchronous optical packets with CMOS circuitry [9].

Figure 2(e) shows a photograph of the prototype router with four input/output ports. The prototype consists of 2U shelves for the optical input/output, the label processors and switches, the shared buffer, and the write-in and read-out OCPTGs (size: 100 x 60 x 100 cm³) [3].

3. Experimental results

Multi-hop operation experiments were performed by using the prototype router with N set to ‘4’. A 10-Gb/s input optical packet (NRZ format, with a 16-bit label including an 8-bit address and a 5-bit TTL-field in front of the 200-ns-long payload with 2⁷-1 PRBS pattern) was generated by a pulse pattern generator (PPG), which is defined as edge node A (Fig. 3 ). The packet was fed to one of the input ports of the router, which serves as a core node. To evaluate multi-hop operation, the packet was looped back to another (or the same) input port, while the route of the packet was switched by changing the address of the label at every hop. When the TTL value reached zero, the packet was forwarded via the discard (TTL = 0) output port to an asynchronous BER tester, which is designated as edge node B. The tester has almost the same structure as the shared buffer, consisting mainly of the all-optical SPC, the OCPTG, and the field programmable gate array (FPGA), which enables BER measurements of asynchronous burst optical packets. In the first set of experiments, the packets without buffering were tested (i.e., the initial TTL value was less than or equal to N-1). Figure 3(a) shows the setup for testing packets after five hops with no buffering performed when the initial TTL value was set to ‘3′ at the PPG. The number shown along each route is the hop count. In the second set of experiments, the shared buffer was used to perform the FEC on the packets after four hops. Figure 3(b) shows the setup for testing packets after nine hops with one-time buffering, where the initial TTL value was set to ‘7’. In this case, the TTL value reached ‘4’ after four hops, and the packet was accordingly forwarded to the shared buffer, in which it was decoded for error correction, stored in the memory, and encoded again with the RS code. Then after the 3R regeneration had been performed, the error-corrected packet was transmitted again through the optical switch. After another four hops (totally eight hops), the TTL value finally reached zero, and hence the packet was tested after totally nine hops with one-time buffering. We used eight lanes of RS code (32, 24) operating on 8-bit symbols. In each lane, two bits out of 16-parallel signals from/into the SPC/PSC (operating at 625 Mb/s) were bound and processed as 8-bit parallel signals (i.e., 8-bit symbols) at ~156 MHz by the FPGA. Sensitivities are defined as the average power of the packet fed to the optical amplifier that precedes the BER tester.

 

Fig. 3 Experimental setups for (a) 1–5 hops and (b) 5–9 hops without and with buffering (FEC), respectively. PPG: pulse pattern generator. BERT: bit error rate tester.

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BER results for the packets before and after buffering are shown in Figs. 4(a) and 4(b), respectively. In both cases, BERs are maintained below the FEC limit (~10⁻³) even after five hops, although power penalties are observed due to the signal-quality degradation. The degradation is mainly caused by the limited bandwidth (BW) of the burst-mode receivers used in the optical switch. In the switch, the burst-mode APD-TIA followed by the discrimination circuit (drive amp) operating at a constant threshold level provides 2R regeneration (i.e., no retiming). Due to the BW limitation of the APD-TIA (~7 GHz at 3 dB), this 2R regenerator causes a pattern-dependent time-shift in rising ‘01’ and falling ‘10’ edges in the packet signal (i.e., phase noise). The magnitude of this shift increases every time the packet passes through the receiver, with a total value reaching about a factor of two (in/out of the switch) multiplied by the hop count. The degradation can be suppressed by using a TWC with higher bandwidth, e.g., an SOA-based optical TWC, which can increase the hop count N before buffering. The packets passing through the buffer after five hops [Fig. 4(b), black] provide almost the same sensitivity (−23.8 dBm at 10⁻¹¹ BER) as those from the PPG [Fig. 4(a), black], which confirms that the error bits are perfectly corrected by FEC and that the PSC of the buffer generates the 3R-regenerated optical packets with almost the same signal quality as the PPG generated.

 

Fig. 4 BER results for packets after (a) 1–5 hops from PPG and (b) 5–9 hops from buffer.

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Figure 5 shows the BER as a function of hop count. The BER gradually increases with hop count, whereas a low enough BER is routinely recovered by FEC at the shared buffer every 4 hops. Eye diagrams taken before and after buffering also show the signal restoration (Fig. 5, insets). Hence, the proposed TTL-based multi-hop transmission scheme using FEC in the shared buffer can expand the number of hops while keeping the BER low. From a theoretical perspective, a powerful FEC process would enable almost an unlimited number of hops at negligible BERs. For example, RS code (255, 239) is a widely used one requiring less coding overhead (i.e., having less error correction ability) compared to the RS code (32, 24) used here but can still be applied to 10-Gb/s, 200-ns packets. RS code (255, 239) is estimated to improve an input BER of ~1 x10⁻⁴ to an output BER of ~5 x10⁻¹⁵ and even with this code, a BER of ~1.25 x10⁻¹³ (~100/4 x 5 x10⁻¹⁵) <10⁻¹² should be maintained after 100 hops by the FEC performed every four hops before the BER reaches ~1 x10⁻⁴. It is also worth mentioning that packet loss due to label-recognition error is not observed (rate <10⁻⁹) because of the high-quality label signal swapped/recreated by the label processor at every hop. The node latency is ~380 ns without buffering and ~1.9 μs with buffering (of which ~500 ns is for decoding/ coding for FEC).

 

Fig. 5 BER as a function of hop count.

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4. Conclusion

Multi-hop operation is enabled by means of TTL-based selective error correction and demonstrated using a prototype hybrid optoelectronic router. The router is realized by combining key optical/optoelectronic device/sub-system technologies and CMOS electronics in a novel architecture. Degraded packets every four hops are successfully restored by the FEC performed at the router’s shared optoelectronic buffer, with the number of hops monitored via the TTL field in the packet label. The multi-hop transmission scheme with the selective FEC function implemented in the buffer enables us to expand the hop count while keeping the packet BER low, which minimizes the electrical processing at the node and avoids the need for optical 3R regeneration at every port of each node. The scheme is thus promising for future low-latency, energy-efficient OPS networks.