Breakdown delay-based depletion mode silicon modulator with photonic hybrid-lattice resonator

Maoqing Xin; Ching Eng Png; Aaron J. Danner

doi:10.1364/OE.19.005063

1. Introduction

Delayed-breakdown diodes have previously been studied for high power electrical switching and pulse generation. In these types of diode, the “breakdown delay” is caused by a superfast impact ionization front propagating at a speed much higher than the saturated carrier drift velocity [1]. In other words, such diodes would normally breakdown, but have insufficient time to do so in this mode of operation. Till now, this technique has not been applied to optical switching and modulation. In this work, we demonstrate that the idea can be applied to integrated optical switching by transiently biasing a depletion mode diode beyond its static breakdown point before breakdown takes place, i.e. breakdown delay-based depletion mode (BDDM) operation. We find high concentration contrast picosecond (ps) level carrier movement can be achieved at the quasi-steady state within either tunneling or avalanche breakdown delay, where only negligible leakage current flow is found. The outstanding electrical performance from the new operation regime can be applied to a miniaturized high electro-optic (EO) sensitivity photonic medium to build an optical modulator with high modulation depth (MD) based on the resonance wavelength shift of a cavity mode in a hybrid photonic crystal (PC) structure. The detailed design of a modulator which is able to take advantage of this operation regime is the subject of the bulk of this article.

By exploiting this unusual operation regime, we are able to demonstrate for the first time the possibility of sub-THz speed modulation with femtojoule (fJ) energy consumption in a silicon integrated modulator which is purely CMOS (complementary metal–oxide–semiconductor) compatible. In particular, the device to be described is built on a hybrid photonic crystal lattice mode gap (HLMG) resonator, where a planar P⁺PNN⁺ diode is embedded in the cavity and is biased under the BDDM operation regime. Compared to rib waveguide based designs, we have found that photonic crystal-based modulators enable faster carrier movement because of a more direct depletion path, which can be combined with the post breakdown operation regime for realizing ps level deep carrier extraction at minimal energy consumption. Additionally, we have optimized the design of the PC cavity to not only create a compact medium with strong optical confinement, but simultaneously optimized the structure with electrical performance in mind. Surprisingly, we have found that a square PC lattice confining the optical cavity enables higher free carrier contrast than a triangular lattice due to the suppressed electrical scattering.

2. Background

Silicon based optical modulators are playing an increasingly important role in optoelectronic integrated circuits (OEIC) [2–5], and have been realized in various photonic media under different operation modes: rib waveguide based Mach-Zehnder interferometers (RWG-MZIs) [6–9], ring resonators (RRs) [10–13], cross waveguide resonators [14], and double heterostructure (DHS) resonators [15]. More recently, nonlinear optic (NLO) organics [15–17] have been studied and 130 GHz bandwidth with negligible energy consumption (<5 fJ/bit) has been demonstrated in PC waveguide-based MZIs (PCW-MZIs) [16]. However, CMOS incompatibility and less developed processing precision, as well as low thermal stability, may limit their potential for low cost, industrial level integration to some extent. Additionally, the switching capability of the reported polymer waveguide is ultimately limited by the slot capacitance, which is essentially comparable to the depletion layer capacitance in a reverse biased diode [7–9,11,12,18] due to the similarity between slot width and dynamic depletion width. Therefore, we believe the answer to low cost, compact sub-THz modulator lies in the combination of depletion mode diodes and highly sensitive photonic media, where the BDDM operation can be applied to push to the performance even further. In Table 1 , a summarized comparison is made between the device studied here and other recently reported silicon integrated modulators. As one can tell, the device proposed here has a much higher potential modulation speed (238 GHz) and more compact footprint (69 µm²) with low energy consumption (26.6 fJ/bit) and acceptable insertion loss (~2.5 dB), but a greater applied voltage is required to drive the diode towards breakdown. It should be noted, however, that in this work our aim is to illustrate the BDDM method, not conduct an in depth comparison of other device types. The purpose of Table 1 is to illustrate what our results indicate is possible from a single designed example only. In the sections that follow, we describe a modulator design in detail such that the performance can be understood physically, and then conduct integrated 3D electrical and optical simulations to judge the potential performance more quantitatively.

Table 1. Comparison of our Device with Recently Proposed Silicon Integrated Modulators

View Table

In our example device, the geometrical dimension of the PC cavity is optimized in terms of optical confinement and EO sensitivity while insertion loss is reduced by introducing insertion stages with tapered group velocity (Section 3.1); additionally, improved carrier movement efficiency is achieved by having a tapered lattice pattern at cavity center with reduced electrical scattering (Section 4). Electrically, a P⁺PNN⁺ diode is embedded in the silicon slab structure with zero aspect ratio, which enables a direct depletion path with minimum carrier momentum loss (Section 3.2). Post breakdown operation is then studied for the first time, where deeper carrier contrast can be achieved without sacrificing device speed or energy consumption due to the quasi-steady state within the breakdown delay (Section 5). Due to the nature of post breakdown operation, higher bias voltage (−15 V) is required for achieving the greatest performance gains, which may add to the design difficulty for driving circuitry. However, it is still possible to reduce the voltage by further improving cavity confinement, EO overlapped volume, or by sacrificing MD.

3. Optical and electrical design

In this section, we describe the basic design of the optical and electrical media where BDDM operation can be realized, as shown in Fig. 1(a) . Optically, the device is based on a 2D PC cavity formed by triangular to rectangular lattice transitions, which is designed in detail in Section 3.1. Electrically, a compact planar electrical diode embedded at the center of the optical cavity for EO index perturbation is described in Section 3.2. The resonance peak of the cavity is located within the near infrared (NIR) range where the optical field intensity at the output side can be modulated by reverse biasing the diode when the resonance peak is red shifted due to the free carrier effect.

Fig. 1 (a) 3D schematic of the device showing the planar HLMG resonator and electrode configuration for external driving signal. (b) The magnified 2D demonstration of the HLMG resonator constructed by hybrid PC lattice transition and additional insertion stages.

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3.1 Optical cavity

The cavity is built on a 2D W1 waveguide, where the air holes (radius r = 123 nm) are completely etched down into the Si layer (thicknessh = 217 nm) in a silicon-on-insulator (SOI) system. The device surface and air holes should be completely passivated by SiO₂ cladding and filled.

The idea of the proposed HLMG resonator is to introduce a photonic mode-gap (PMG) by sandwiching a rectangular lattice (PC2, lattice constant $a_{2}$ ) within a hexagonal lattice (PC1, lattice constant $a_{1} = 410 nm$ ). The resultant cavity can provide strong confinement in the x direction for waveguide defect modes whose frequencies lie within the PMG (guided modes in PC2 but evanescent modes in PC1). To improve optical confinement in the y direction, an additional transitional lattice (TL, three periods) is inserted between PC1 and PC2 to guarantee a smooth spatial field variation, and therefore, provide a high proximity to Gaussian-like mode envelop, which has been previously recommended for realizing high Q slab cavities [19,20]. A top view of the resonator is shown in Fig. 1(b), where the central three columns of PC1 (dashed red circles) are shifted towards the defect center to provide a smooth transition from a hexagonal to a rectangular lattice [21]. The hole displacement in the x direction is linearly tapered over the TL periods according to the relationship, where $Δ x_{n}$ is the displacement of the n^th column (TL_n) from the adjacent PC1. In the y direction, the lattice constant is homogeneous to satisfy the lattice matching condition.

Then, the cavity is optimized in terms of EO sensitivity $η_{EO}$ , which is defined as the modulation depth achieved per square index change. According to the detailed mathematical calculations in Appendix A, $η_{EO}$ is found proportional to ${(Q / V_{mod})}^{2}$ for a specific material system and operating wavelength (Q and $V_{mod}$ are quality factor and mode volume respectively). In Fig. 2(a) , the defect period $a_{2}$ is first studied and is kept at 400 nm for maximized $Q / V_{mod}$ . Then, the transverse electric (TE)-like mode band diagram of the mode gap cavity is calculated by the 3D plane wave expansion (PWE) method and plotted in Fig. 2(b), where the waveguide defect mode is found blue-shifted when the lattice deforms from hexagonal to rectangular through the TL layers, which opens up a mode gap $Δ f = 7.3 THz$ near the projected Brillouin zone edge (scaled up for $a_{1} = 410 nm$ ). According to our 3D FDTD calculation, a resonance mode is found at 1606 nm with high optical confinement: $Q = 6146$ and $V_{mod} = 0.79 (λ / n)^{3}$ , shown in Fig. 3(a) . The normalized resonance frequency is located slightly lower to the mode gap (offset is ~20% of the mode gap) shown in Fig. 2(b), which can be caused by numerical inaccuracies probably due to the lattice resolution of the unit cell used in the PWE method. The mode profiles shown in Fig. 3(b) and 3(c) indicate two separated field maxima located symmetrically at the PC1-TL boundaries. Each field maximum follows a Gaussian-like mode envelop due to the TL periods and therefore, only a small amount of out-of-plane radiation is detected in Fig. 3(c).

Fig. 2 (a) The defect lattice constant a₂ is selected at 400 nm for optimized cavity confinement and EO sensitivity. (b) The projected band diagram shows a wide mode gap between PC1 and PC2, which is the origin of the highly confined optical cavity resonance.

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Fig. 3 (a) Transmission spectrum of the HLMG resonator indicates a highly confined resonance mode in the NIR range. (b) 2D profile of the resonance mode in the xy plane. (c) 2D profile of the resonance mode in the xz plane.

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Finally, since the HLMG cavity would normally have high insertion loss due to a group velocity mismatch between the PC waveguide and a conventional ridge waveguide, an additional insertion stage (PC3) has been designed for use between the ridge waveguide and PC1 for a smooth group velocity transition, as illustrated in Fig. 1(b). Two approaches were previously proposed about the design of the tapering stage: reduced hole radius [22] and increased lattice constant [15,23]. To avoid the fabrication error usually related to patterning smaller feature sizes, the latter approach is used here. In Fig. 4 , both lattice constant $a_{3}$ and the number of tapered periods are studied. It is shown the insertion efficiency is about 3% (−15 dB) without tapered lattices (i.e. $a_{3} = a_{1}$ ) and can be enhanced to 56% (−2.5 dB) by 6 periods of PC3 when $a_{3} = 450 nm$ , where the defect modes of PC1and PC2 at resonance frequency are shifted to the fast light regime from the slow light regime. The result found is consistent with previous studies on PCW injectors with tapered lattice constant [15].

Fig. 4 Significantly improved insertion efficiency is detected with 6 periods of PC3 when a₃ is kept at 450 nm.

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3.2 Electrical diode

Electrically, a P⁺PNN⁺ diode is created at the cavity center for free carrier based index modulation. It is shown in Fig. 5(a) that the diode is designed asymmetrically in size and dopant concentration with P region extended off center by 117 nm to take advantage of the higher free carrier coefficient of the holes. The highly conductive P⁺/N⁺ regions are defined by 10²⁰ cm⁻³ boron/phosphorous impurities for driving the diode externally while P/N regions are doped to $N_{p}$ = 3 × 10¹⁸ cm⁻³ and $N_{n}$ = 9 × 10¹⁸ cm⁻³ respectively. The diode width covers 7 periods of SiO₂ holes in the x direction to include only the two resonance field maxima of the cavity mode shown in Fig. 3(b) and 3(c), which makes a total dopant area as compact as 14 µm². This design is to achieve a maximized overlapped volume between the EO active region and the optical mode while at the same time keep the impurity loss within an acceptable level (~2.3 dB for the dopant level specified above). It is important to note that in this work, the planar design of the diode is adopted by using a silicon slab (zero aspect ratio) rather than a high aspect ratio rib waveguide [8,11,12]. As compared in Fig. 5(b) and 5(c), this design will facilitate more efficient carrier depletion/extraction from the central active region by removing the sharp sidewall corners as barriers. Therefore, the carriers take a direct depletion route without significant loss in their momentum when reaching the P⁺/N⁺ side. The same condition applies to the recovery of the carriers at the center of the P/N region with the release of the external bias. We believe this is also one of the major reasons for the much higher switching speed achieved in our device.

Fig. 5 (a) 2D schematic of the lateral P⁺PNN⁺ diode embedded in the HLMG cavity. yz cross section of the embedded diode shows (b) indirect carrier depletion path in a rib waveguide based diode (not recommended) and (c) direct depletion path in the planar diode design that we employ instead.

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4. Reduced electrical scattering by lattice transition

The main advantage of the HLMG resonator described in Section 3 over previously studied DHS resonators [15,19] is that the electrical scattering of the free carriers can be reduced by the rectangular lattices located at the center of the cavity. Although PC-based silicon free carrier modulators have been studied quite extensively [24], the scattering effect of the embedded PC holes/columns to the momentum of the free carriers is still not fully explained either experimentally or theoretically. We demonstrate in this work that the significance of this undesired scattering is dependent on the lattice pattern of the PC and is large enough to be taken into consideration when predicting free carrier profile under reverse bias. To achieve that, the following work is carried out by using a physically-based model from ATLAS [25], which predicts carrier distribution and I-V response of a PC-embedded diode by solving Poisson’s and the continuity equations in a 3D temperature-dependent dielectric-insulator-conductor environment. The major physical effects for a reverse biased diode are included in the simulator, which includes concentration dependent mobility (CDM), field dependent mobility (FDM), Shockley-Read-Hall (SRH) and Auger recombination, concentration dependent lifetime (CDL), bandgap narrowing (BGN), band-to-band tunneling (BTBT), and the Selberherr impact ionization (SII) model. The asymmetric P⁺PNN⁺ diode in Fig. 5(a) is reverse biased by a DC voltage swept from 0 to −8 V. In Fig. 6(a) , the hole concentration probed near the waveguide center (x = 0, y = −50 nm, z = 0) is plotted for PC free, HLMG and DHS embedded diodes. The dimension of the DHS cavity is kept according to ref [15], where the central cavity is formed by one period of hexagonal lattice with a slightly larger lattice constant (a₂ = 420 nm). It is shown that although much shallower carrier depletion is found in either PC embedded diodes compared to PC free design, carriers are extracted from the P/N region more efficiently for the HLMG cavity at the same bias voltage compared to others. This may come from the different gradients of quasi-Fermi levels (within the depletion region) as well as drift mobility μ of the free carriers in the two cavities. According to Matthiessen’s rule [26]

\frac{1}{μ} = \frac{m^{*}}{q} (\frac{1}{τ_{m i}} + \frac{1}{τ_{m o}})

where q and

m^{*}

are electron charge and carrier effective mass respectively;

τ_{m o}

is the mean free time corresponding to the major scattering events (phonon, impurity, etc.) while

τ_{m i}

is introduced here as the mean free time corresponding to the additional insulator scattering. We postulate the lower scattering effect in the HLMG cavity increases

τ_{m i}

and therefore carrier mobility assuming similar phonon/impurity scattering in both cases. The collective effects are the higher carrier contrast and uniformity. The latter is demonstrated in Fig. 6(b) and 6(c) for a bias voltage of −8 V, where almost homogenous carrier distribution is found in the HLMG cavity in the x direction while in the DHS cavity, a periodically modulated carrier concentration is found in the same direction. The periodicity of the carrier modulation matches that of the embedded PC lattice and therefore can be clear evidence for free carrier scattering and compensation due to the embedded PC lattices.

Fig. 6 (a) Static carrier level near the center of the waveguide shows different hole contrasts at the same bias voltage for diodes embedded in different lattice patterns. 2D hole profiles at −8 V indicate in the x direction (b) highly uniform carrier distribution for the HLMG cavity and (c) periodically modulated concentration for the DHS cavity.

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5. Electro-optic modulation

In this section, we demonstrate that much higher speed and carrier contrast can be achieved under BDDM operation regime than previously studied depletion mode modulators [8,11,12]. To investigate this post breakdown operation, transient characterization is used to show the dynamic carrier evolution since static (DC) solution to the Poisson’s and continuity equations is no longer available. For consistency, the same set of physical models and effects in Section 4 are included in the 3D transient simulator. In Section 5.1, the physical origin of the breakdown delay and the I-V characteristics of the depletion diode within the delay period are discussed in detail. Also, carrier distribution within the depletion region under reverse bias is analyzed for high speed modulation purposes. In Section 5.2, the device speed and energy consumption are characterized by a return-to-zero (RZ) binary sequence with a peak-to-peak voltage large enough for BDDM operation. Moreover, the theoretical upper limit of the device in this configuration is analyzed.

5.1 Post breakdown analysis

In Fig. 7(a) , a negative voltage step is applied to the device for duration much larger than the transit time of the diode. The carrier concentration is probed at the same location as in Section 4. The amplitude of the step is swept from −6 V to −18 V to include all operation regimes of the reverse biased diode. It is shown for low voltage steps $V_{over} = - 6 V$ and, stable carrier concentration jumps are detected which indicate conventional DC carrier depletion can be achieved when the voltage is kept much lower than the static breakdown point of the diode. As the magnitude of the reverse step increases to −12 and −15 V, the depleted carrier level only holds for a finite duration before it jumps back to and stays at a higher level. This process can be understood as device breakdown mostly due to a band-to-band tunneling process caused by the bandgap narrowing effect. The critical breakdown field $E_{m}$ at the depletion region probed is 1.2 MV/cm which is slightly smaller than the theoretical value predicted in Si abrupt junctions [26]:

E_{m} = \frac{4 \times 10^{5}}{1 - (1 / 3) \log_{10} (N / 10^{16})}

where N is the dopant concentration of the P region (the lightly doped side in the one-sided abrupt junction). According to Eq. (2), a reduced critical field can be caused by the embedded intrinsic PC lattice which reduces the effective dopant level of the P/N region by a factor proportional to the filling ratio of the holes. As the voltage step further increases to −18 V, the DC carrier depletion is even less stable and completely compromised by the avalanche multiplication process after a short period. The carrier analysis of the post breakdown operation is confirmed by the leakage current results shown in Fig. 7(b), where appreciable and significant current flows are detected in tunneling and avalanche breakdown conditions respectively.

Fig. 7 (a) A finite breakdown delay time is found in the post breakdown operation regime where the carrier level can be further depleted with increase of the bias voltage. (b) The leakage current is found to be negligible within the breakdown delay and increases drastically after breakdown takes place.

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Optically, this decreased (or temporally instable) carrier contrast is undesired since it will lead to reduced (or fluctuating) ON/OFF transmission contrast which may in turn result in a higher bit error rate (BER) in pseudo random binary sequence (PRBS) based communication systems. However, still in Fig. 7(a), a finite breakdown delay is detected during which the carrier contrast still increases with the magnitude of the reverse voltage at the same carrier transition speed. We call this quasi-steady state since it follows the static behavior of the diode under pre-breakdown bias. At a bias voltage of −18 V, for example, the carrier contrast is 6 × 10¹⁷ cm⁻³, which is 2 times the value at −9 V for the same location. Moreover, negligible leakage current (~-10 nA) is found within the breakdown delay in Fig. 7(b). Therefore, it is possible to transiently bias the device beyond its static breakdown point within the delay for a deeper carrier depletion level without sacrificing either switching speed or energy consumption. In the tunneling breakdown case, the breakdown delay $Δ t_{BT}$ is measured to be 16 ps, which is associated with the tunneling time of the free carriers governed by the time dependent Schrodinger equation in semiconductor nanostructures [27]. For the avalanche breakdown case, the delay time $Δ t_{BA}$ is much shorter (~7 ps) and is usually interpreted as the avalanche build-up time, which is caused by the high voltage ramp $d V_{over} / d t = 1.8 \times 10^{14} V/s$ from unbiased to reverse biased operation [1]. The voltage ramp needs to satisfy the critical condition (Eq. (3)) in order to excite superfast impact ionization fronts travelling in a velocity that exceeds the saturated drift velocity of free carriers (usually v_s = 1.1 × 10⁷ cm/s) [28]:

d V_{over} / d t > 2 v_{s} \sqrt{q N_{B} (V_{bi} - V_{over}) / 2 ε}

whereqand

N_{B}

are the electron charge and dopant concentration of the base region where fronts propagate through, respectively;

V_{bi}

andεare the built-in potential of the junction and permittivity of the material, respectively. For biasing our device around −18 V, the critical voltage ramp is calculated as ~1.5 × 10¹³ V/s.

In this work, we choose to bias our device in the tunneling breakdown regime for two practical concerns. First, the carrier contrast within the tunneling delay is strong enough to guarantee significant MD in the optical part (10 dB is used as a benchmark for ON state definition); and second, the tunneling delay $Δ t_{BT}$ is about 8 times longer than the carrier rise time (~2 ps) and therefore safe enough for transmitting a binary sequence of up to 8 consecutive “1”s in a multi-GHz PRBS system without degeneration in signal-to-noise ratio (SNR), whose probability is less than 0.5⁸ = 0.4% . Unlike injection mode EO modulators, the carrier distribution is usually not uniform within the depletion region of the reverse biased diode due to the continuously bent quasi-Fermi levels. Therefore, it is necessary to investigate carrier profile within the active region and interpret it into the corresponding index profile for optical transmission study. In Fig. 8(a) and 8(b), 2D hole profiles are shown in the xy plane (z = 0) and yz plane (x = 0) at V_over = −15 V for the quasi-steady state before breakdown. Both carrier profiles indicate a well-presented depletion belt whose width is slightly modulated in the x direction with the periodicity of the embedded PC lattice while uniform in the z direction with the homogeneous electrical medium. To precisely measure the location and width of the depletion region, a 1D cutline is made along the y direction at x, z = 0 for both holes and electrons. In Fig. 9(a) , the hole/electron cutline under bias is plotted against the zero bias condition to demonstrate the externally modulated depletion width with respect to the bias voltage, which follows the theoretical model

W_{D} = W_{D p} + W_{D n} = \sqrt{\frac{2 ε (N_{p} + N_{n})}{q N_{p} N_{n}} (V_{bi} - V_{over} - \frac{2 k T}{q})}

It is shown in Fig. 9(a) that the total depletion width increases from 50 to 120 nm when the diode is biased to −15 V. The hole/electron concentration contrast is highly dependent on the y coordinate due to the smooth concentration tails at the boundaries of the depletion region. The peak carrier contrast is detected at y = −80 and y = −125 nm for holes and electrons, respectively, as shown in Fig. 9(b), where the electron contrast peak is higher due to the higher

N_{n}

. However, the hole contrast covers a wider range with the full width half maximum (FWHM) pulse width

W_{FWHM p}

= 35 nm (

W_{FWHM n}

= 28 nm) due to the lower

N_{p}

. Compared with the mode profile in Fig. 3(b), it is clear that the carrier contrast peaks are completely covered by the optical field maxima. Therefore, it is possible to further improve the EO sensitivity of the cavity by increasing the depletion width of the diode, which can be achieved by lowering the dopant level of the P/N region.

Fig. 8 Magnified 2D hole profiles at −15 V indicate the depletion region (a) in the xy plane and (b) in the yz plane.

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Fig. 9 (a) 1D cutline of the hole/electron concentration along the y direction indicates the depletion width movement at −15 V bias. (b) 1D carrier contrast profile between 0 and −15 V within the depletion region.

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5.2 Performance characterization

The dynamic performance of the device is characterized by a voltage pulse with pulse width smaller than the breakdown delay of the diode for quasi-stable carrier depletion. Due to the non-uniform carrier profile in the xy plane, the carrier movement is probed at different locations throughout the active region (within the plane of z = 0). First, $V_{over}$ is kept at −15 V. It is shown in Fig. 10(a) that the carrier evolution is identical in the x direction while in the y direction, the carrier contrast varies and agrees with the distribution in Fig. 9(b). More importantly, the rise/fall time (10% to 90%) of the carrier transition is almost the same at $t_{r} = t_{f} = 2.1 ps$ regardless of the probe coordinate, which corresponds to a uniform switching speed of 238 GHz of the device. For depletion mode EO modulators, the upper limit of the device speed $f_{U L}$ is partially determined by the time constant of the equivalent RC circuit, as shown in Fig. 10 (b):

f_{U L} \equiv \frac{1}{t_{r} + t_{f}} \approx \frac{1}{4.4 τ_{R C}} = \frac{1}{4.4 (R_{p +} + R_{p} + R_{n} + R_{n +}) C_{D}} \approx \frac{W_{D}}{4.4 ε (ρ_{e f f p} L_{p} + ρ_{e f f n} L_{n})}

where

C_{D}

and

R_{p,}_{n}

are the depletion layer capacitance and P/N region resistance respectively;

W_{D}

is given in Eq. (4).

R_{p +,}_{n +}

can be neglected since it is much smaller than

R_{p,}_{n}

. Therefore, higher device speed may be achievable with a reduced

C_{D}

by lowering the P/N dopant level. However, this would be compensated by an increased P/N effective resistivity

ρ_{e f f p, n}

. Another way of improving speed is to reduce the dopant length of the P/N region

L_{p, n}

, and overall transmission can be reduced as a tradeoff due to the extended P⁺/N⁺ region.

Fig. 10 (a) The transient carrier response at different locations of the depletion region at −15 V indicates uniform switching speed of 238 GHz. (b) Equivalent RC circuit of the embedded P⁺PNN⁺ diode. (c) Tradeoff relationship between MD and bias voltage among different operation regimes.

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$V_{over}$ is swept from 0 to −15 V to study the tradeoff relationship between bias voltage and MD. At each voltage step, the 2D carrier profile (both for holes and electrons) is interpreted into the index profile for the optical simulator to measure resonance peak shift and transmission contrast. According to Fig. 10(c), while 11 dB ON/OFF contrast can be achieved at −15 V, it is still possible to reduce the voltage to −9 V for a slightly degraded contrast at 7 dB, where the device works at the conventional depletion regime with a similar speed, Fig. 7(a).

Then, the device is biased with a 238 GHz RZ signal with V_pp = 15 V, as shown in Fig. 11(a) . In Fig. 11(b), the carrier is probed at the center of the waveguide to represent the uniform device speed while the relative transmission and overall current flow are shown in Fig. 11(c) and 11(d). The transient carrier variation and the corresponding transmission evolution indicates a deeply modulated (MD>10 dB) optical signal from the red shift of the resonance peak. In Fig. 11(d), the capacitive I-V characteristic is found at both 0-1 and 1-0 voltage transitions. Since the bit duration here is much longer than the transit time of the diode and yet shorter than the breakdown delay, the AC current cuts off at the end of each bit in a similar way to a step recovery diode (SRD), where abrupt corners are found as carrier depletion reaches the quasi-stable level. Finally, since energy consumption only happens at the 0-1 transition where both current and voltage are non-zero, the averaged energy consumption of the device is calculated as 26.6 fJ per bit through Eq. (6) [18]

Fig. 11 (a) The applied 238 GHz RZ voltage signal switching between 0 and −15 V. (b) The representative hole response at the center of the waveguide. (c) The 3D FDTD interpreted transmission evolution of the HLMG resonator corresponding to (b). (d) The transient current flow of the device at voltage transitions.

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E_{bit} = 1 / 4 \int_{0 - 1} V_{over} I_{over} d t

Due to the material nature of silicon photonic devices, the modulator proposed in this work suffers from thermal-optic instability as dn/dT = 1.8 × 10⁻⁴ K⁻¹. The temperature fluctuation may happen both internally or externally. According to the calculated ultra-low energy consumption, the localized heat generation will be at minimum, and mainly concentrated in the EO active region where carrier movement takes place. The heat generated may red shift the resonance peak of the cavity for both ON and OFF state due to the thermal-optic effect. In that case, the operation wavelength needs to be modified accordingly to compensate for the thermal-optic resonance peak shift in order to maintain the modulation depth. Externally, on the other hand, the high Q cavity based design inevitably results in a narrow optical bandwidth around the full-width half maximum (FWHM) peak width. Therefore, the resonance peak will be sensitive to either environmental temperature fluctuations or fabrication errors. In the former case, a temperature controller can be used to curb the temperature shift within an acceptable range. For the latter, the OFF state voltage is not necessarily kept at 0 V and can be pre-calibrated to pull back the resonance wavelength to its designed value. Depending on the amount of red or blue deviation of the peak spectral position, a positive or negative DC voltage can be applied to the bias tee to compensate for the fabrication imperfections. Then, the device can be driven by the new non-return-to-zero (NRZ) signal with a slightly modified V_pp.

6. Conclusion

A compact silicon optical modulator has been introduced that functions within a new BDDM operation regime, which enables much higher carrier speed and extraction efficiency with minimum current flow. This mode of operation can be realized in a planar P⁺PNN⁺ diode embedded hybrid lattice resonator for integrated optical modulation in pure silicon. The demonstrated device speed is as high as 238 GHz at the cost of 26.6 fJ/bit energy consumption. The operation mode combined with the miniaturized photonic medium can eventually lead to the realization of high speed silicon modulation components in a high density photonic integrated circuit (HDPIC) and work towards the goal of green photonics.

Appendix: EO sensitivity of a cavity resonator for high speed modulation

Generally, for cavity resonator based intensity modulators, the dependence of EO sensitivity on optical confinement and the embedded EO active region is analyzed as follows. Assuming a Gaussian shape for the resonance peak, we have

P_{OFF} (ω) = A e^{- {(ω - ω_{0})}^{2} / 2 σ^{2}} Δ ω_{FWHM} = \frac{ω_{0}}{Q} = 2.35 σ

where A and $ω_{0}$ are the peak transmission and resonance frequency at the OFF state respectively. When the device is biased, the resonance peak shifts to. At the ON state, transmission at $ω_{0}$ and MD are calculated as

P_{ON} (ω_{0}) = A e^{- {(ω_{0} - ω_{0}')}^{2} / 2 σ^{2}} MD= 10 \log [P_{OFF} (ω_{0}) / P_{ON} (ω_{0})] = 5 \log e \cdot {(ω_{0} - ω_{0}')}^{2} / σ^{2}

where $ω_{0} = 2 π C / λ_{0}$ and $λ_{0}$ is the vacuum wavelength. For optical mode perturbation in a microcavity system, the following condition applies:

λ = λ_{0} / n_{eff} = 2 L_{cav} / k Δ n_{eff} \approx Δ n V_{ol} / V_{mod}

where $L_{cav}$ is the cavity defect length andkis an integer; $Δ n_{eff}$ is the effective index change of the cavity mode between ON and OFF states and $Δ n$ is the absolute index change of the EO active medium, e.g. free carriers, NLO organics; $V_{ol}$ is the overlapped volume between EO active medium and cavity mode distribution. Here, the effective index approximation is used to relate $Δ n_{eff}$ to localized index change. By inserting Eq. (7) and (9) into Eq. (8) and defining EO sensitivity as $η_{EO} = MD / Δ n^{2}$ , one arrives at the following:

η_{EO} \approx {(\frac{3.5}{n_{eff}})}^{2} {(\frac{Q}{V_{mod}})}^{2} V_{ol}^{2}

The first term on the right hand side of Eq. (10) is nearly fixed for a given material system and operating wavelength, e.g. NIR operation in a silicon PC waveguide; the second term represents the optical confinement of the resonance medium; and the last term is partially the electro-optic coupling efficiency which can be engineered separately through the configuration of the embedded EO active medium. Although $η_{EO}$ increases monotonously with $Q^{2}$ , the quality factor of a practically useful resonator should be capped at ~10⁴ for sub-THz transmission capacity in NIR regime due to the photon lifetime limitation $τ_{p h} = Q / ω_{0}$ ( $ω_{0}$ is the resonance frequency).

Acknowledgement

This work was supported in part by Singapore’s A*Star Science and Engineering Research Council (SERC) grant 0921010049. The authors acknowledge the technical support from SILVACO International, Singapore and thank Dr. Soon Thor Lim from IHPC, A*Star, Singapore for helpful discussions.

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	RWG-MZI (depletion)		RR (depletion)		Micro-disk (depletion)	Dual RR (injection)	PCW-MZI (polymer)	HLMG (BDDM)
Ref.	[8]	[7]	[11]	[12]	[18]	[13]	[16]	This work
Footprint^a (µm²)	3 × 10³	4.2 × 10³	1 × 10³	~100	~20	~300	80	45/69^c
Speed	12.5Gb/s	40 Gb/s	11 GHz	19 GHz	10 Gb/s	>40Gb/s	130 GHz	238 GHz
V_pp (V)	8	6	2	10	3.5	6	1	15
Energy (fJ/bit)	-	-	50	−1 µA^b	85	300	<5	26.6
MD (dB)	6	1.1	6.5	5	8	~10	-	10
Insertion loss (dB)	2.5	0.5	2	-	~1.5	0.5	<4	>10/2.5^d

Breakdown delay-based depletion mode silicon modulator with photonic hybrid-lattice resonator

Abstract

1. Introduction

2. Background

3. Optical and electrical design

3.1 Optical cavity

3.2 Electrical diode

4. Reduced electrical scattering by lattice transition

5. Electro-optic modulation

5.1 Post breakdown analysis

5.2 Performance characterization

6. Conclusion

Appendix: EO sensitivity of a cavity resonator for high speed modulation

Acknowledgement

References and links

Cited By

Figures (11)

Tables (1)

Equations (10)

Optics Express