1. Introduction

A macrochip is envisioned as the integration of many chips, such as processor chips and memory chips, for much enhanced performance [1]. Such macrochips cannot function well without high-bandwidth, high-density, low-latency and low-power interchip and intrachip optical communication networks. Various Si-photonic network topologies have been proposed [1–4]; all of them require massive waveguide routing. With large-scale integration, the waveguide routing length could easily be 10s of cm and might approach 100cm for some long links, which demands ultralow-loss (<0.1dB/cm) routing waveguides. Another desirable feature of the routing is high-density, including tightly spaced parallel waveguides and tight bends. In addition, if the waveguide routing is implemented on a single photonic layer [2–4], waveguide crossings will become an essential element. Although waveguide crossings can potentially be made very low loss (~0.1dB) and low crosstalk (−40dB) [5], they present severe constraints to network scaling as a massive number of crossings may be needed for single-layer routing. One way to avoid this problem is to use multilayer routing [1], which avoids waveguide crossings but needs interlayer optical couplers [6–7]. If each link uses 4 or less interlayer hops, the optical loss due to the interlayer coupling can potentially be contained within 10 dB.

The high refractive index contrast of Si waveguides greatly enhances scattering loss at the core-cladding boundary. The typical loss of sub-micron Si waveguides is around 2dB/cm. To achieve much lower loss, one can either make the core very small [8], so that most of the optical mode field spreads into the waveguide cladding, or make the core very large combined with a shallow ridge [9–10], so that most of the field is confined within the Si core. Both approaches aim to minimize the optical overlap with the boundary. Wet oxidation and stripping can also be used to smooth waveguide sidewalls [11]. A third method is to eliminate the etched sidewall by using selective oxidation to form the waveguide [12–13]. All these methods have achieved Si waveguides with a loss of 0.1-0.5dB/cm. To further lower waveguide loss, one can use silica or SiN waveguide deposited on Si substrate. These waveguides use very weak optical confinement with large mode size (>10μm) and can result in a loss of 0.1dB/m [14]. All the above low-loss waveguides are distinctly different from the sub-micron Si waveguides that are typically used by other active/passive optical devices; therefore they are not suitable for single-photonic-layer-routing architectures. For multilayer routing, the following monolithically integrated components have yet to be demonstrated using the above-mentioned low-loss waveguide methods: 1) compact interlayer coupler with low-loss coupling to the photonic device layer using sub-micron waveguide; 2) low-loss tight bends; and 3) tightly spaced parallel waveguides with low crosstalk.

In this paper we report 300nm thick SOI waveguides that have achieved a mean loss of 0.026 dB/cm with a variance of 0.0056 dB/cm while constrained to a commercial 130nm CMOS manufacturing line. Combined with monolithically integrated tight bends and compact interlayer grating couplers, they complete a toolbox for ultralow-loss, high-density multilayer waveguide routing for macrochip interconnects.

2. SOI waveguide design

Our waveguide was fabricated on SOI substrates with 300nm thick Si. The etching depth was specified to be 220nm to enable tight bends and compact, high-speed ring modulator devices [15] with controlled free-spectral ranges [16] in the same process. Different widths were designed for different waveguides: 300nm for single-mode straight waveguides, 380nm for compact ring waveguides and tight bends, and 3μm for ultralow-loss routing waveguides. The 3μm-wide waveguides are only used in the straight routing sections. When a waveguide route changes direction, it first tapers from 3μm down to a width of 380nm, then undergoes a 90-degree L-bend, and tapers from 380nm back out to a width of 3μm. The taper is 50μm long; the 90-degree L-bend has a 20μm radius, with curvature changing continuously from zero to 1/15 μm⁻¹ then back to zero. This waveguide routing configuration ensures that only the fundamental mode will be excited in the 3μm multimode waveguide, while allowing tight bends (L-bend, S-bend, etc) with very small bending loss.

The dominant loss mechanism in a ridge Si waveguide is typically the scattering loss at the etched sidewalls [11–12]. The top and bottom surfaces of the Si layer are much smoother and thus do not contribute appreciable loss. As shown in Fig. 1(a) , the fundamental TE mode in the 3μm wide waveguide is confined in the center, far away from the sidewalls. The simulation result in Fig. 1(b) shows that the field intensity at the sidewall in the 3μm wide waveguide is 400 times smaller than in the 300nm wide waveguide, hence making it possible to achieve potentially ultralow loss, while also allowing high-density routing. The simulation result in Fig. 1(c) indicates that two parallel waveguides with 5μm center-to-center spacing will have negligible crosstalk after 10cm propagation.

 

Fig. 1 (a) Fundamental TE mode of the 3μm multimode waveguide. (b) Normalized TE mode field intensity at waveguide sidewall vs. waveguide width. (c) Crosstalk vs. center-to-center spacing between two parallel 3μm-wide waveguides after 10cm propagation.

Download Full Size | PDF

To test propagation loss in the waveguides, we designed structures with long overall lengths. In the structure shown in Fig. 2 , long spiral waveguide loops are laid out at the four edges of a 8x8 mm² die. The inset pictures (a) and (b) show the enlarged views of the bottom-right corner, where we can see the L-bends and the tapers. Two grating couplers with 0.5 mm spacing were used to couple light between optical fibers and the waveguide loops. We designed similar test structures in the same die with identical bends and tapers but with different multimode waveguide lengths (10 cm, 60 cm and 100 cm) so that the propagation loss could be accurately extracted.

 

Fig. 2 Waveguide loss test structure. Waveguides are green colored.

Download Full Size | PDF

3. Waveguide test results

Our waveguides and other devices were fabricated in Freescale’s 130nm SOI CMOS process. We have full-flow wafers that went through the complete front-end and backend processes; we also have passive-split wafers that were pulled out from the fab right after waveguide etching, field oxide deposition, and chemical-mechanical polishing. The full-flow wafers have multiple metal and dielectric layers on top while the passive-split wafers only have thin native oxide atop the Si waveguides. Passive-split and full-flow wafers were processed together in the same process until the passive-split wafers were pulled out. Each 8-inch wafer has up to 48 reticles.

Since our grating couplers only support TE optical mode, our test data described here are for TE mode only. Figure 3(a) shows the measured loss spectrum of the three multimode waveguide test structures. Losses due to grating couplers at the input and output ends of the test structures have been calibrated out. Each structure has 106 L-bends and 210 tapers, which caused 3-4 dB loss over the tested spectrum. Propagation loss in the multimode waveguide section can be readily extracted from the data shown in Fig. 3(a). We have tested both single-mode and multimode waveguides on different wafers. Figure 3(b) shows the extracted loss from multiple reticles and on different wafers. On the same passive-split wafers, the single-mode waveguide loss is ~2dB/cm, while the multimode waveguide loss is much lower (~80X) due to the reduced mode overlap with sidewalls, which is in accordance with our numerical analysis. Another observation is that waveguides on the passive-split wafers have much lower propagation loss and lower variance than the waveguides on the full-flow wafers. One possible reason is that the full-flow wafers have gone through many more steps of processing including multiple thermal cycles, which may have caused extra stress and defects in the Si waveguides. Another possible factor is that full-flow wafers have multiple dielectric layers on top of the waveguides, which may result in additional scattering and/or absorption losses. This suggests that passive-split wafers are more suitable for low-loss long-distance routing as required for the macrochip [1]. The 68-reticle test data in Fig. 3(c) shows that the mean propagation loss in multimode waveguides on the two passive-split wafers is approximately 0.026dB/cm. Based on the simulations, we believe that this waveguide loss is no longer dominated by the waveguide sidewall roughness; instead it is mainly from the defects in the Si layer and in the interface between the Si and the buried oxide. Therefore, further significant improvement may require higher quality of SOI wafers.

 

Fig. 3 (a) Measured loss spectrum of the three waveguide test structures with different multimode waveguide lengths. Grating coupler losses have been calibrated out. (b) Multi-reticle multi-wafer test data for single-mode and multimode waveguides on different wafers. The loss is averaged value over the wavelength. (c) Histogram of 68-reticle test data of multimode waveguide loss on two passive-split wafers, showing mean value of 0.026dB/cm and standard deviation of 0.0056dB/cm.

Download Full Size | PDF

4. Conclusions

We have demonstrated ultralow-loss silicon optical waveguides up to one meter long, fabricated in a 300nm thick SOI CMOS process. The loss is 0.026dB/cm averaged over 68 reticles across two 200mm wafers. We have previously demonstrated 2.8dB interlayer coupling loss using 25μmx40μm sized grating couplers [7] fabricated in the same process, with further improvements anticipated. Combined with the low-loss (estimated to be ~0.01dB) tight bends, we have now demonstrated a complete toolbox for ultralow-loss high-density waveguide routing for macrochip interconnects.