1. Introduction

The silicon nanophotonic platform based on a silicon-on-insulator (SOI) substrate enables the dense photonic integration due to the transparency for light propagating and ultra-high refractive index contrast for the light confinement. A typical silicon nanophotonic waveguide can support the light propagating at wavelength of 1.55 μm with a thickness of 200~300 nm [1, 2]. To enable a photonic system on silicon including active devices, such as lasers, detectors and optical amplifiers, integrating direct-band III-V semiconductor optoelectronic materials on the SOI substrate through a wafer-scale/die bonding technology was demonstrated recently [3–16]. For Si/III-V photonic integration, the two fundamental issues need to be considered are effective light amplification/absorption of the Si/III-V waveguide and efficient optical coupling to the silicon photonic layer through a compact optical vertical interconnect access [3, 4].

The Si/III-V evanescent laser/photodetectors reported in Refs [5–9]. consists of a silicon micro-waveguide under the III-V semiconductor layer and the light is basically confined in the silicon waveguide. The evanescent field in the bonded III-V semiconductor layer is utilized for amplification or absorption, which has a limited light confinement factor in the active region. To improve the efficiency of device, Refs [4, 10, 11]. proposed and demonstrated a hybrid waveguide structure, of which both the III-V semiconductor layer and SOI layer are etched to form a hybrid waveguide and the super-mode of the hybrid waveguide can be either basically confined in the III-V or silicon depends on the width of the SOI waveguide. To transfer the light from the III-V to silicon, a coupling length of 120 μm is required in the Ref [11]. This method improves the confinement factor in the active region for effective light amplification/absorption. However, it requires the silicon waveguide to have a relatively large cross-section so that it can have a comparable effective index as the III-V semiconductor waveguide on the top to couple the light down, which makes it not suitable for the silicon nanophotonic platform of which the SOI layer has a thickness of 200~300 nm.

For the silicon nanophotonic platform, different heterogeneous integration schemes are demonstrated in Refs [12–16]. The III-V semiconductor layers are integrated on silicon based on a BCB bonding and the light is coupled from the active device to the SOI layer through a polymer mode-size converter or resonant coupling. For the case of resonant coupling, the coupling efficiency is very low due to the effective index mis-match between the III-V semiconductor waveguide and thin SOI waveguide. Very recently the optical interconnect access through tapering the III-V semiconductor waveguide and SOI waveguide in an opposite direction was proposed in Ref [16]. It shows that a tapering region ~100 μm is required for a sufficient light coupling and an ultra-thin BCB layer is required in the fabrication as the thickness of the BCB bonding layer will affect the coupling length significantly.

In this paper, a new Si/III-V heterogeneous integration structure based on a direct wafer-bonding [9], which does not require the BCB process, and the optical vertical interconnection access for the light coupling to the silicon nanophotonic platform is proposed and designed (see Fig. 1 ). Figure 1(a) gives the cross-section of Si/III-V waveguide. The III-V semiconductor layers are bonded to the SOI layer (which is 220 nm in our design example) and thinned down to a thickness of ~2 μm, which consists of a p-cladding layer on top, two separate confinement hetero-structure (SCH) layers sandwiching a 100 nm thick active region (the active region is a multiple quantum wells and barrier layers in practice), and a thin n-cladding layer at the bottom. The III-V semiconductor thin-film is then etched till the n-cladding layer to form a waveguide confining the light laterally (in the x-direction). Different from the structures mentioned above, there is no SOI channel waveguide/air trench/BCB underneath the III-V semiconductor thin-film in the proposed structure, which can give a better thermal management. Section II gives a detailed design of Si/III-V waveguide to maximize the light confinement factor in the active region, which gives a confinement factor of ~24% in the 100 nm-thick active region for a 1.5 μm wide Si/III-V waveguide. This ensures an effective light amplification/absorption of active photonic devices based on this integration platform.

 

Fig. 1 Schematic view of the heterogeneous photonic integration and optical vertical interconnect access; (a) cross-section of the waveguide; (b) side-view of structure and light coupling between the silicon layer and heterogeneous waveguide structure; (c) taper structure of the SOI layer; (d) tapering structure of the III-V on silicon.

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To efficiently couple the light between the silicon nanophotonic waveguide and Si/III-V waveguide (see Fig. 1(b) for the side view), the III-V semiconductor waveguide and silicon substrate are tapered simultaneously in the same direction as shown in Fig. 1(c) and Fig. 1(d). This optical coupling structure is different from the existing structure presented in Ref [16], in which the silicon waveguide was inversely tapered in the opposite direction as the III-V semiconductor waveguide tapering direction. To optimize the tapering structure of the silicon waveguide and III-V waveguide for an efficient coupling, a two-dimensional approximated model is employed after applying the effective index method in x-direction, which converts the tapering structure into a graded refractive index profile along the z-direction and reduce the computational time consuming in the optimization significantly. The optimization example presented in Section III shows ~100% coupling efficiency with a 25 μm long tapering region, which is much shorter as compared to the structure reported in Ref [10,11,16]. This light coupling between the silicon nanophotonic layer and Si/III-V waveguide is numerically verified by a parallel three-dimensional finite-difference-time-domain (FDTD) simulation, which also shows that this structure has a good fabrication tolerance allowing ± 500 nm between the III-V and SOI layer for a coupling efficiency>90%.

2. Si/III-V waveguide design for effective light amplification/absorption

For the Si/III-V waveguide structure proposed in Fig. 1(a), an optical design of III-V wafer structure on silicon and Si/III-V waveguide width is implemented to maximize the light confinement in the active region for an effective light amplification/absorption. As a design example, the silicon-on-insulator substrate has a 220 nm thick silicon layer (refractive index 3.477) on a 1μm thick buried oxide layer (refractive index: 1.45). The InP based epitaxial wafer to be bonded on the silicon has respective refractive index of 3.17, 3.52, 3.46 for the p(n)-cladding layer, active region and SCH layer based on a similar material composition as shown in Ref [7]. The active region in the design example has a thickness of H_a = 100 nm. The n-cladding layer bonded to the SOI has a thickness of 140 nm. The confinement factor in the active region can be maximized through optimizing the thickness of the two SCH layers.

Using a multilayer planar waveguide eigenmode solution developed in-house, the confinement factor ${\Gamma }_a$ in the active region (defined as ${\Gamma }_a=\frac{{\displaystyle {\int }_{H_a}{\left|E_x\right|}^{2}dy}}{{\displaystyle \int {\left|E_x\right|}^{2}dy}},$ where H_a is thickness of the active region) for the transverse electric (TE) mode (main electric component E_x is in the x-z plane) is calculated under different thickness of the two SCH layers, in which the confinement factor is presented in Fig. 2(a) and it shows the maximal light confinement factor is 22.5% when the top and bottom SCH layer has a respective thickness of 80 nm and 120 nm. The corresponding refractive index profile and the mode profiles are presented in Fig. 2(b), which shows the field profile has a good overlap with the active region.

 

Fig. 2 (a) Contour plot of confinement factor in the active region under different thickness of two SCH layers; (b) Refractive index profile of the optimized multilayered waveguide for a maximal light confinement in the active region and the corresponding mode profile.

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After bonding the III-V semiconductor layers to the SOI substrate as shown in the inset of Fig. 2(a) and thinning down (removal of the InP substrate), the III-V semiconductor is etched till the n-contact layer to form the Si/III-V waveguide. The width of the III-V waveguide section plays a crucial role in determining the light confinement for the three-dimensional waveguide structure in practice. With the finite-difference full-vectorial eigenmode solution, the TE mode of the Si/III-V waveguide is calculated under different width of the waveguide. Figure 3(a) gives the light confinement factor in the 100 nm thick active region under different width of the waveguide, which suggests the width of the III-V waveguide should be no less than 1μm for a sufficient light confinement in the active region. Figure 3(b)–3(e) gives the corresponding eigenmode profile when the width of the waveguide is 0.5 μm, 0.7 μm, 0.9 μm and 1.5 μm, respectively. It shows when increase the width of the Si/III-V waveguide, the confined light will “move up” to the III-V semiconductor layers.

 

Fig. 3 (a) Confinement factor Γ_a in the 100 nm thick active region; (b-e) Eigenmode profiles of the Si/III-V waveguide calculated by finite-difference full-vectorial eigenmode solution; when (b) w = 0.5 μm; (c) w = 0.7 μm; (d) w = 0.9μm and (e) w = 1.5 μm.

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In our following design, the waveguide width is chosen to be 1.5 μm and it has a confinement factor of ~24% in the 100 nm thick active region.

3. Optimal design of waveguide tapering for optical vertical interconnect access

The optical vertical interconnect access for transferring the light between the Si/III-V waveguide and silicon nanophotonic layer is realized through tapering the III-V waveguide and silicon waveguide in the same direction as shown in Fig. 1. The optical mode profiles shown from Fig. 3(b) to Fig. 3(e) suggest that when reducing the width of the III-V waveguide, the light beam will be “pushed down” to the SOI layer. However, a direct optimization of the tapering including length and shape using the three-dimensional waveguide structure is tremendously time consuming.

To simplify the optical design, an approximated two dimensional modal in the y-z plane is used after applying the effective index method in the x-direction as illustrated in Fig. 4 . The tapering structure in the three-dimensional model is represented by a gradual refractive index in the two-dimensional model in the y-z plane as shown in the bottom of Fig. 4.

 

Fig. 4 (a) The tapering structure of the three-dimensional waveguide is approximated by a two dimensional modal slab waveguide in the y-z plane after applying the effective index method in the x-direction. The tapering structure is represented by a gradual refractive index in the two-dimensional model in the y-z plane as shown in the bottom; (b) Tapering shape considered in the optimization.

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For the III-V semiconductor waveguide and SOI waveguide in the tapering section, a tapering shape formulated with $W(z)=w_0+(w_1-w_0){\left(\raisebox{1ex}{$z$}\!\left/ \!\raisebox{-1ex}{$L_t$}\right.\right)}^{\alpha }$ is considered in the optimal design (see Fig. 4(a)), where $L_t$ is the tapering length, $w_0$ is the waveguide width at the narrow end and $w_1$ is the waveguide width at the wide end. The parameter $\alpha$determines the shape of the tapering as shown in Fig. 4(a). The tapering structure is optimized through minimize the overlap integral between the eigenmode of Si/III-V waveguide $E_f(y)$and the propagating field $E(y,z)$, which starts from the eigenmode of silicon nanophotonic waveguide, $C\left(z\right)={\left|\frac{{\displaystyle \int E(y,z)E_f\left(y\right)dy}}{{\displaystyle \int E_f(y){\overline{E}}_f\left(y\right)dy}}\right|}^2.$

As a design example, we choose the tapering length to be 25 μm and the corresponding contour plot of the coupling efficiency is presented in Fig. 5(a) , which shows when ${\alpha }_{Si}=0.4$ and ${\alpha }_{InP}=1.4$, the coupling efficiency reaches the maximal value 0.9945. The tapering structure for the silicon and III-V semiconductor layers are shown in Fig. 5(b). It can be seen that there is air-trench under the III-V semiconductor layers, which ensures a better thermal dissipation compared to the case when there is a channel silicon waveguide under the III-V semiconductor layer. For this tapering structure, the propagation of light from the silicon waveguide to the III-V semiconductor layers is shown in Fig. 5(c) with the two-dimensional model. The full-vector three-dimensional simulation shown later agrees well with this two-dimensional approximated model.

 

Fig. 5 (a) Contour plot of coupling efficiency under different tapering parameter (α) when the tapering length L = 25 μm; (b) optimized tapering structure; (c) light propagation simulation of the optimized structure.

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For different tapering lengths, the optimization of the tapering shape is carried out and Fig. 6 gives the coupling efficiency under the propagation distance for these optimized structures (different tapering lengths). The simulation shows even when the tapering length goes down to 15 µm that the coupling efficiency is still about 97%, which is much shorter as compared to the tapering length reported in Refs [10,11,16]. It also can be seen from the simulation result, once the light is coupled to the Si/III-V waveguide, it propagates along the Si/III-V waveguide without coupling back to the silicon layer, which indicates the designed tapering structure is an adiabatic coupling structure.

 

Fig. 6 Coupling coefficient along the propagation distance for different tapering lengths, which shows an adiabatic coupling and a coupling efficiency ~97% even when the tapering length is only 15 µm.

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To verify the above design with the approximated two-dimensional model, a full-vector three-dimensional finite-difference-time-domain simulation (3D-FDTD) is carried out, which utilizes the parallel computing based on message-passing-interface. The influence of the mis-alignment $\Delta s$(as shown in the inset of Fig. 7 ) between the III-V semiconductor layer and silicon photonic layer on coupling efficiency is also studied. Transmission under different alignment accuracies are given in Fig. 7 using the 3D FDTD simulation. The corresponding field profiles at the Si/III-V waveguide cross-section when the mis-alignment $\Delta s$is 0 µm, 0.1 µm, 0.25 µm and 0.5 µm. The simulation results not only verify the optimal design presented above but also shows a coupling efficiency >90% when the alignment accuracy is within ± 0.5 µm.

 

Fig. 7 (a) Transmission of the designed structure under different alignment offset (based on 3D FDTD simulation); (b-e) Field profile at the Si/III-V waveguide cross-section simulated by FDTD when Δs = 0 µm (b); Δs = 0.1 µm (c); Δs = 0.25 µm (d); Δs = 0.5 µm (e).

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5. Conclusion

We have proposed and designed a new heterogeneous Si/III-V integration and the optical vertical interconnect access to the silicon-on-insulator nanophotonic layer. The III-V semiconductor layers are directly bonded to the SOI layer and etched to form the Si/III-V waveguide, which has no air-trench or SOI channel waveguide underneath. Our design example has shown that a 1.5 μm wide Si/III-V waveguide has a confinement factor of ~24% in a 100 nm-thick active region for effective light amplification/absorption.

To transfer the light between the Si/III-V waveguide and SOI nanophotonic waveguide, the III-V semiconductor waveguide and SOI layer are tapered in the same direction. An optimization of the tapering structure using simple two-dimensional model after applying effective index method has been presented, which gives ~100% adiabatic coupling efficiency with a 25 μm long optical vertical interconnect access. The three-dimensional finite-difference-time-domain electromagnetic simulation has verified the design numerically and also shows this structure has a good fabrication tolerance allowing ± 500 nm between the III-V and SOI layer for a coupling efficiency>90%.