1. Introduction

Silicon Mach-Zehnder modulators (MZMs) have been well developed as a key component in Si integrated photonic circuits (Si-PICs), however, they usually suffer from a long active length on the order of millimeters due to the relatively weak free-carrier dispersion effect in Si as well as the small overlap between the optical mode and the region of carrier-density changes in either metal-oxide-semiconductor (MOS) or pn configurations based on the conventional Si waveguides [1]. It is highly desired to shorten the active length to micrometer scale for high-density PICs in which thousands of modulators will be integrated [1]. A potential approach for this purpose is to utilize nanoplasmonics because of its capability of tight optical confinement well beyond the diffraction limit [2]. Several kinds of plasmonic modulators, which modulate the intensity and/or the phase of a surface plasmon polariton (SPP) signal propagating along the metal/dielectric interfaces by an external control excitation, have been proposed [3]. However, most of them rely on active materials other than Si, e.g., polymers [4], BaTiO₂ [5], or indium-tin-oxide (ITO) [6, 7] etc., which are not complementary MOS (CMOS) compatible. A MOS type plasmonic modulator reported by Dionne et al uses Si as the active material, but its vertical Ag-oxide-Si-Ag geometry requires a non-standard CMOS technology for fabrication [8].

On the other hand, many kinds of plasmonic waveguides along with various waveguide-based passive components have been proposed and/or demonstrated recently [9]. Among them, a horizontal metal-insulator-Si-insulator-metal plasmonic waveguide integrated in silicon-on-insulator (SOI) platform is an attractive candidate because it provides a tight optical confinement and it is fully CMOS compatibility when Al or Cu is used as the metal [10, 11]. Various passive components based on the Cu-SiO₂-Si-SiO₂-Cu waveguide have been seamlessly implemented in Si channel waveguide based PICs using standard CMOS technology [12]. More importantly, its metal-oxide-semiconductor geometry inherently allows a voltage applying between the metal cover and the Si core to modulate its propagation property, namely, to realize an active control. An electro-absorption (EA) modulator based on this plasmonic waveguide has been experimentally demonstrated [13], but its modulation depth is limited by the breakdown voltage of the gate oxide between the Si core and the Cu cover. In this work, we demonstrate that the modulation depth under a certain driving voltage can be significantly improved by utilizing the phase modulation of the plasmonic waveguide.

2. Operating principle

The horizontal Cu-insulator-Si-insulator-Cu plasmonic waveguide shown schematically in Fig. 1(a) allows a voltage to be applied between the Cu cover and the Si core to modify the free carrier distribution in the Si core. Figure 1(b) plots electron distributions in the Si core (n type, 5 × 10¹⁸ cm⁻³) in the conditions of depletion, flat-band and accumulation, respectively. In the depletion condition, a depletion width W_dep ($\propto N_D{}^{-0.5}$, where N_D is the doping density in the Si core) can be defined and the distribution can be approximated as a step function (shown as the blue dash line in Fig. 1(b)). In the accumulation condition, the electron concentration maximizes at ~3-5 Å away from the SiO₂/Si interface due to the quantum mechanical effect and then decreases to N_D quickly with the distance from the interface increasing. As a first approximation, the distribution can be approximated as a step function (shown as the black dash line in Fig. 1(b)) and an accumulation layer (AcL) can be defined with width of t_AcL and average concentration of N_AcL ($=\frac{{\epsilon }_0\cdot {\epsilon }_d}{e\cdot t_{ox}\cdot t_{AcL}}(V-V_{FB})$, where ε₀ is the vacuum permittivity; ε_d is the relative permittivity of the gate dielectric; e is electronic charge; t_ox is the gate oxide thickness; V is the applied voltage; and V_FB is the flat-band voltage). The achievable N_AcL depends on the breakdown voltage of the gate dielectric, and it can be larger than 10²⁰ cm⁻³ for modern CMOS devices. The complex index of Si with such a large free electron concentration (i.e., larger than 10²⁰ cm⁻³) should be estimated using the well-known Drude model [13, 14].

 

Fig. 1 (a) Schematic of the proposed horizontal Cu-insulator-Si-insulator-Cu plasmonic waveguide integrated on SOI platform, a voltage can be applied between the Cu cover and the Si core to modify the free carrier distribution in the Si core, (b) Electron distributions in a metal-insulator-Si (n-type, 5 × 10¹⁸ cm⁻³) capacitor in the conditions of accumulation, flat-band, and depletion. As a first approximation, an accumulation layer (AcL) is defined in the accumulation condition, which has t_AcL = 1 nm and N_AcL proportional to the applied voltage.

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The modal index of the horizontal Cu-SiO₂-Si-SiO₂-Cu waveguides, i.e., the real effective index (n_eff) and the propagation loss (α) in dB/μm, are calculated at 1550 nm using the eigenmode expansion (EME) method. The structural parameters are set as follows: Si core height = 340 nm, Si core width W_P = 10–100 nm, SiO₂ gate oxide thickness t_ox = 1–10 nm, t_AcL = 1 nm, and N_D = 5 × 10¹⁸ cm⁻³ (thus W_dep = 16.3 nm). The complex refractive indices of Cu, SiO₂, and Si at 1550 nm are set as follows: Cu: 0.282 + i11.048 [15], SiO₂: 1.445, Si in depletion: 3.455, and Si with 5 × 10¹⁸ cm⁻³ n-type doping: 3.4506 + i0.001232. The complex index of Si in AcL is read from Fig. 2(b) of Ref [13]. Figure 2(a) shows the electric field (E_x) distribution for a plasmonic waveguide with W_P = 50 nm and t_ox = 2 nm. In order to see the profile more clearly Fig. 2(b) plots the field profiles along x-axis at the middle of the height in the conditions of depletion and accumulation (with N_AcL = 6 × 10²⁰ cm⁻³). In the depletion condition the ratios of the optical intensity inside the 2-nm-thick SiO₂ gate and the 50-nm-wide Si core are 29.9% and 67.9% respectively. In the accumulation condition the ratios of the optical intensity inside the 2-nm-thick SiO₂ gate, the 1-nm AcL, and the 48-nm-wide remaining Si core are 28.8%, 6.6%, and 62.2% respectively. One sees that the ratio of the optical intensity inside the SiO₂ gate decreases slightly due to the light confined inside the AcL increasing. Figure 3 plots the calculated Δn_eff and Δα (compared to that in the depletion condition) as a function of N_AcL for plasmonic waveguides with different dimensions. We can see that both Δn_eff (negative) and Δα increase almost exponentially with N_AcL increasing. The plasmonic waveguides with thinner t_ox and narrower W_P provide larger Δn_eff and Δα, thus larger modulation efficiency, but they also suffer from larger initial propagation loss (i.e., α in the depletion condition) and larger coupling loss to the input/output Si waveguide (not shown here), namely larger insertion loss (IL).

 

Fig. 2 (a) The calculated electric field (E_x) distribution in a plasmonic waveguide with 50-nm Si core and 2-nm SiO₂ gate dielectric, (b) The normalized E_x distributions at the middle of the height in the conditions of depletion and accumulation. One sees that the field in the 1-nm AcL is enhanced greatly.

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Fig. 3 The calculated modification of the real part of modal index (left axis) and the propagation loss (right axis) in the horizontal Cu-SiO₂-Si-SiO₂-Cu plasmonic waveguides as a function of N_AcL of the 1-nm-thick AcL: (a) The SiO₂ thickness ranges from 1 to 10 nm when the Si core width keeps 50 nm, (b) The Si core width ranges from 10 to 100 nm when the SiO₂ thickness keeps 2 nm.

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An EA modulator based on Δα has been experimentally demonstrated [13]. However, it suffers from a tradeoff between IL and extinction ratio (ER) at a certain N_AcL, which depends on the applied voltage and is limited by the breakdown voltage of the gate dielectric. For example, for a plasmonic waveguide with t_ox = 2 nm and W_P = 20 nm, the propagation loss in the depletion condition α(dep) is 1.747 dB/μm and that in the accumulation condition with N_AcL = 6 × 10²⁰ cm⁻³ α(accu) is 3.302 dB/μm. An EA modulator based on this plasmonic waveguide with length of L_P = 3 μm gives IL = 5.24 dB and ER = 4.67 dB.

As shown in Fig. 3, n_eff is also significantly modified by N_AcL, which could be used to design a phase modulator. Two well-known structures for converting phase variation into intensity variation are Mach-Zehnder interferometer (MZI) and ring resonator [1]. Although submicrometer ring resonator based on the plasmonic waveguide has been demonstrated [16], it suffers from low Q-value and tough fabrication tolerance for the aperture coupler between the ring and bus waveguides. Therefore, a conventional asymmetric Si MZI is used in this work. The plasmonic phase modulator is inserted in one arm of the MZI. The output power (normalized by the input power) through the MZI can be expressed as [17]:

 

Fig. 4 Calculated transmission spectra for an asymmetric Si MZI with ΔL = 1550 μm and one arm inserted by a plasmonic phase modulator with t_ox = 2 nm, W_P = 20 nm, and L_P = 3 μm in the conditions of depletion and accumulation with N_AcL = 6 × 10²⁰ cm⁻³.

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3. Design and experiment

The proposed plasmonic phase modulators are fabricated on SOI wafers using standard CMOS technology. As a primary device for proof-of-concept, an n⁺-doped Si pad is used to connect the Si-core which is doped by 5 × 10¹⁸-cm⁻³ phosphorus, as shown schematically in Fig. 5(a) . The Si core of the plasmonic waveguide has width of W_P and length L_P, connected to the 0.5-μm-wide Si channel waveguide through tapered couplers with length L_C = 1 μm. The Si core of the couplers are also surrounded by a thin gate oxide and a thick Cu layer as the Si core of the plasmonic waveguide, thus their propagation property is also modified by the applied voltage. We may define an effective L_P-eff which has a value between L_P and L_P + 2L_C to include the coupler’s effect. Then, the above equations are still valid to replace L_P by L_P-eff. The detailed fabrication process flow for these devices has been reported elsewhere [13]. Figure 5(b) is a picture of the fabricated device, showing two Al electrodes connected with the Cu cover and the n⁺-Si pad, respectively. This device is inserted in the shorter arm of an asymmetric Si MZI with ΔL of ~1550 μm, as shown in Fig. 5(c). For comparison, this device is also inserted in a single Si channel waveguide to behave as an EA modulator, as shown in Fig. 5(d). Figure 6(a) is the cross-sectional transmission electron microscopy (XTEM) image of the final device, showing both the Cu covered Si core and the Al covered Si pad. Figure 6(b) is the enlarged XTEM image of the Si core of the plasmonic waveguide, showing that the bottle-shaped Si core is surrounded by a ~6.2-nm SiO₂ layer formed by rapid thermal oxidization and covered by a thick Cu layer formed by Cu sputtering and Cu plating [12]. The electric field (|E_x|) profile in this plasmonic waveguide at 1550 nm is shown in Fig. 6(c), obtained by the EME method. The calculated n_eff and α are 2.626 and 0.881 dB/μm, respectively. The ratios of optical intensity inside the Si core, the SiO₂ gate, and the other area (mainly in the bottom SiO₂) are 37.6%, 55.4%, and 7.0% respectively.

 

Fig. 5 (a) Schematic layout of the plasmonic modulator, the tapered coupler length L_C is 1 μm and the plasmonic waveguide length L_P ranges from 1 to 10 μm, (b) Picture of the fabricated plasmonic modulator showing two Al electrodes, (c) An asymmetric Si MZI with the plasmonic modulator inserted in its shorter arm, (d) A single Si waveguide with the plasmonic modulator inserted to behave as an EA modulator.

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Fig. 6 (a) XTEM image of the final device, (b) Enlarged XTEM image around the Si core of the plasmonic waveguide, (c) The corresponding electric field (|E_x|) profile at 1550 nm obtained using EME method, the calculated n_eff is 2.626 and α is 0.881 dB/μm, close to the measured value of ~0.58 dB/μm.

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The diced chips are measured using the conventional fiber-waveguide-fiber method. The input light is transverse electric (TE)-polarized light from a broadband laser (~1520–1620 nm). The chip contains straight plasmonic waveguides (without doping and Al electrode) with L_P ranging from 1 to 500 μm (L_C keeps 1 μm). Figure 7(a) shows the measured output power of these straight plasmonic waveguides (normalized by that of the reference Si waveguide without the plasmonic structure), from which the propagation loss and the coupling loss (between the plasmonic waveguide and the Si channel waveguide) are extracted to ~0.58 dB/μm and ~0.93 dB/facet respectively using the conventional cutback method, close to the theoretical prediction and the previous report [11]. More measurement shows that the Si pad with two orthogonal Si channel waveguides causes ~1.0 dB additional loss, and the 5 × 10¹⁸-cm⁻³ phosphorus doping and Al contact causes another ~0.4 dB loss. Therefore, the total IL for a plasmonic waveguide with L_P = 1 μm is ~3.8 dB. The current-voltage curves measured on the devices exhibit typical MOS capacitor characteristics, as shown in Fig. 7(b) for devices with L_P = 1 and 2 μm. The gate leakage current density is ~3 A/cm² at 6 V, much larger than the theoretical prediction for the 6.2-nm thermal oxide. The breakdown occurs around 6–7 V and the longer devices usually have a slightly smaller breakdown voltage. After breakdown the devices have a large gate leakage current in the range of 0.1–1 mA. The observed electrical properties can be attributed to the present of thinner SiO₂ at the top and corner of the Si core, as seen from Fig. 6(b). The oxide capacitance C_ox ($=A\cdot \frac{{\epsilon }_0\cdot {\epsilon }_{SiO2}}{t_{ox}}$, where A is the active area) is calculated to ~11 fF for the device with L_P = 1 μm and ~188 fF even for the device with L_P = 50 μm, too small to be measured experimentally as it is companied with the relatively large gate leakage current.

 

Fig. 7 (a) Output power measured on the straight plasmonic waveguides, normalized by that of the reference Si waveguide without the plasmonic structure, propagation loss and coupling loss are extracted from the linearly fitting, (b) I-V characteristics of the devices with L_P = 1 and 2 μm, the breakdown voltage is ~6-7 V.

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4. Results and discussion

Figure 8 plots output spectra of an EA modulator with L_P = 3 μm under a voltage ranging from 0 to 8V, normalized by that of a reference Si waveguide without the plasmonic structure. The modulation is almost wavelength independent and the 3-dB modulation is obtained at ~6–7 V bias, similar to the previous result [13].

 

Fig. 8 Transmission spectra measured on an EA modulator with 3-μm L_P under voltage ranging from 0 to 8 V, normalized by the spectrum measured on a reference Si waveguide without the plasmonic structure.

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Figure 9 plots output spectra measured on a MZI modulator with 1-μm L_P under a voltage ranging from 0 to 6 V. They exhibit typical resonant properties with FSR of ~0.45 nm. Upon a voltage applied, the spectrum is red-shifted and its amplitude is reduced, in agreement with the theoretical prediction read from Fig. 4. We can see that the shift is small at low voltage while it becomes large when V is further increased, which is because Δn_eff increases with N_AcL almost exponentially, as shown in Fig. 3. The typical ERs are 6–10 dB at 6-V bias, much larger than the corresponding EA modulators. Figure 10 depicts normalized output powers versus voltage for MZI modulators with L_P = 1, 2, and 3 μm at some specific wavelengths. At these selected waveguides a large ER of 12–18 dB is obtained. As the abovementioned, the modulation depth can be further improved simply by a proper MZI design to make two arms having similar loss or to modify the coupling ratio at the input of the MZI to balance the difference in loss such that equal optical powers enters the MZI output coupler.

 

Fig. 9 Transmission spectra measured on a MZI modulator with 1-μm L_P device under voltage ranging from 0 to 6 V.

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Fig. 10 Normalized output power versus voltage for MZI modulators with different L_Ps at some certain wavelengths. They provide much larger modulation efficiency than the corresponding EA modulator at the price of narrower optical bandwidth.

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Figure 11 shows ac response of a MZI modulator with 1-μm L_P under 0–6 V square voltage swing with frequency of 10 kHz and 10 MHz. It exhibits 9-dB ER at 10 kHz and 2.4-dB ER at 10 MHz due to a relatively large rise and fall time of ~3 μs. This large rise and fall time can be attributed to the long distance between the Si-core and the n⁺-contact for the present device, as shown in Fig. 4(a). It is ~8-μm long and is perpendicular to the Si core, thus resulting in long transport time on the order of tens of ns and large load resistance on the order of tens of kΩ, thus resulting in the slow speed.

 

Fig. 11 Ac responses of a 1-μm-L_P MZI modulator under 0–6 V voltage swing with frequency of 10 kHz and 10 MHz. The relatively low speed of the present modulator is attributed to the long distance between the Si-core and the n⁺-contact, thus a significant improvement could be expected by the structural optimization.

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In the above measurement, we make sure that the devices are measured before breakdown, i.e., the voltage is less than or equal to 6 V and the gate leakage current is below 1 μA. After breakdown, the devices still work but the gate leakage current increases rapidly to the 0.1–1 mA range, as shown in Fig. 7(b). Before breakdown we believe that the EO effect (which leads to a negative index change) dominates as we observe in Fig. 9 that the spectral peaks are red-shifted, although the thermo-optic (TO) effect (which leads to a positive index change) may also exist. After breakdown, we believe that the TO effect dominate due to the large current, as we really see that the spectral peaks are blue-shifted (not shown here) as well as the reduced ERs at >6 V bias observed in Fig. 10.

The apparent two main issues of the present modulator are the large drive voltage requirement (which already approaches to the breakdown voltage and leads to a relatively large gate leakage current) and the low speed. The first issue arises from the relatively small achievable N_AcL when SiO₂ is used as gate dielectric. Numerical simulation suggests that this issue can be solved, at least alleviated, by using a high-κ dielectric. First, a high-κ dielectric can provide a large achievable N_AcL at a certain voltage. Second, a high-κ dielectric usually has a large reflective index, for example, HfO₂ has κ of ~25 and n of ~1.87, and TiO₂ has κ-value of ~40 and n of ~2.2 [18, 19]. Numerical simulation shows that a certain N_AcL can provide large Δn_eff and Δα when n of the insulator in the metal-insulator-Si-insulator-Si plasmonic waveguide becomes large. For instance, for a Cu-TiO₂(2 nm)-Si(20 nm)-TiO₂(2 nm)-Cu plasmonic waveguide, numerical simulation predicts that the 6 × 10²⁰-cm⁻³ N_AcL gives Δn_eff of 0.237 and Δα of 2.629, compared to Δn_eff of 0.135 and Δα of 1.555 for the SiO₂ counterpart. The required voltage (V – V_FB) for the 6 × 10²⁰-cm⁻³ N_AcL is 0.54 V for the 2-nm TiO₂ gate dielectric and is 5.57 V for the 2-nm SiO₂ gate dielectric.

For the second issue, the solution is to shorten the distance between the n⁺-contact and the Si-core. A suitable configuration is to use a rib Si waveguide and place the n⁺-contact on the Si slab parallel to the Si-core. The carrier transport time ($\propto d/\nu$, where d is the distance and ν is the electron saturation velocity) will be the order of 10 ps if the distance is reduced to less than 1 μm. The modulator speed will be limited by the RC constant. As the abovementioned the oxide capacitance is ~11 fF for the device with L_P = 1 μm. The other capacitance (including the Si slab contact pad and the Cu metal over the waveguide) depends on the detailed structure and may roughly be assumed to have the same magnitude. Thus the total capacitor will be less than 100 fF owing to the ultracompact size of the modulator. The resistance includes the impedance of the signal source R_s ( = 50 Ω) and the lump resistance of the modulator R_mod which also depends on the detailed structure. If R_mod is assumed to have the same magnitude as R_s, the total resistance will be ~100 Ω. Then, the RC limited bandwidth ($=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2\pi RC$}\right.$) is estimated to ~16 GHz. This value can be further improved by the structural optimization. Moreover, RF power is predicted to be ~5 fJ/bit when the voltage is reduced to ~1 V and the gate leakage current is below the nA range.

5. Conclusion

In summary, a fully CMOS compatible Si plasmonic phase modulator based on the horizontal Cu-insulator-Si-insulator-Cu nanoplasmonic waveguide are proposed and experimentally demonstrated. It exhibit large ER as compared to the corresponding EA modulator. Although the present devices require large drive voltage and exhibit slow speed, these issues could be solved by using a suitable high-κ dielectric as the insulator and by the structural optimization to reduce the distance between the n⁺-contact and the Si core.