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Abstract: We report an 850-nm vertical cavity surface emitting laser (VCSEL)-based optical link that achieves a new record in speed. The laser driver and receiver ICs are fabricated in standard 90-nm bulk CMOS, and the optoelectronic devices are commercial components. Operation at 30 Gb/s with a bit-error rate < 10−12 is achieved, representing to the authors’ knowledge the highest speed reported to date for a CMOS-based full optical link. Transmitter feed-forward equalization is shown to improve maximum data rate from 25 to 30 Gb/s, timing margin by 17% at 23.5 Gb/s, and receiver sensitivity by 4 dB at 23.5 Gb/s.
©2013 Optical Society of America
1. Introduction
Short reach optical links based on multimode fiber (MMF) and vertical cavity surface emitting lasers (VCSELs) target applications in data-com and computer-com. Modern supercomputers capable of 1015 operations per second permit computation-intensive research in many areas of engineering, science, and national security. This level of performance is only capable with a high capacity communication network between thousands of microprocessor cores to permit efficient computation. Future machines capable of more than 1018 operations per second will demand higher performance networks characterized by lower power consumption, lower cost, and higher bit rate. At higher bit rates, the practical length of electrical interconnects decreases, which when combined with decreasing costs of optics leads to a possibility of optical interconnects supporting most off chip communications in future machines. It’s expected that power efficiency better than 1 pJ/bit and cost below $0.10/Gb/s will be required to support exascale machines by 2020 [1,2].
VCSEL links over MMF are commonly used for several reasons. VCSELs can be fabricated using micrometer scale lithography, which has been made inexpensive from extensive research and development for IC manufacturing over the past three decades. Given vertical light emission, VCSELs can also be burned in and tested at the wafer level. This reduces costs dramatically as suboptimal VCSELs, both individually and in arrays, can be identified and discarded before being diced and packaged. The series resistance of a VCSEL is also often close to 50 Ω, which allows a direct connection with the transmitter IC without a complicated matching network. Finally, VCSELs can be directly modulated, which cuts down the complexity and power consumption associated with external modulation [3].
The size and numerical aperture of MMF cores match well to a VCSEL’s output. Coupling can be accomplished using passive alignment and simple injection molded optics, which reduces production costs. The fiber’s bandwidth is sufficient for short reach links. Assuming launch conditions that meet the encircled flux standards, OM2 fiber is characterized to support a minimum of 500 MHz-km, which can support 10 Gb/s Ethernet over an 82 m link. More recent OM4 fiber has the same 50 µm core diameter, but has an effective bandwidth of 4700 MHz-km to support 100 Gb/s over 125 m [4].
Feed-forward equalization (FFE) is commonplace in transmitters for electrical links to compensate for the physical bandwidth limitations inherent to copper interconnects [2]. The underlying concept is to pre-distort the transmitted signal to improve the bandwidth of the link. High-pass drivers can improve the bandwidth of the driver-VCSEL combination, enabling transmission at higher data rates [6,7]. Equalization can also simultaneously improve bit rate, receiver sensitivity, jitter, and power efficiency in optical links [3,8]. These links make use of transmitter pre-distortion to compensate for bandwidth limitations through the entire link as opposed to seeking improvements in the laser output alone.
Previous works in this area have explored the tradeoffs between power consumption, bit rate, and density [3,5]. The highest bit rate achieved using 90 nm CMOS ICs was 28.5 Gb/s in a link using a transmitter with FFE paired with a high-speed receiver using inductive peaking for bandwidth extension. The same link also achieved a best power efficiency of 1.5 pJ/bit at 22.5 Gb/s. That receiver paired with a transmitter without FFE showed a maximum bit rate of 25 Gb/s and best power efficiency of 1.78 pJ/bit at 17.5 Gb/s [3]. The receiver reported in [5] achieved a maximum bit rate of 25 Gb/s and minimum power efficiency of 2.6 pJ/bit at 15 Gb/s using a transmitter without equalization.
The highest serial data rates demonstrated by VCSELs at BER < 10−12, are 55 Gb/s using equalization [9] and 44 Gb/s without equalization [10] at 850nm, 49 Gb/s at 980nm (−10°C) [11], 40Gb/s at 1100nm [12], and 35Gb/s at 1550nm [13]. It is important to note that most of the record VCSEL modulation results [10–13] are obtained with test equipment driving the laser and test equipment for the O/E conversion (e.g. a reference photodiode or receiver) and not complete TX-RX optical links such as we report here.
In this paper, we describe a VCSEL-based MMF optical link using 90 nm CMOS circuits that achieves a maximum bit rate of 30 Gb/s – to the authors’ knowledge the highest rate achieved in a VCSEL-based MMF link driven by CMOS to date. The link is made from a transmitter reported in [3] and a receiver reported in [5] and all characterization results reported here were obtained on testing the TX-RX pair together. This link uses FFE to improve the bit rate, power efficiency, sensitivity, and timing margin characteristics compared to the non-equalized link result in [5] that incorporated the same receiver. Equalization is shown to dramatically improve link quality at bit rates that approach the maximum link capacity, while at lower data rates equalization becomes less effective and is not needed.
2. Optical link design
The optical link is shown in Fig. 1(a). The transmitter consists of a two-stage current-mode-logic (CML) differential pre-amplifier followed by split main and post cursor paths as reported in [3]. The post-cursor path uses a chain of amplifiers to act as a delay, which are followed by the post-cursor tap driver. The main cursor is buffered by a single amplifier before the main cursor driver. All amplifiers are differential current mode logic (CML) stages with inductive peaking for bandwidth extension. The VCSEL, which is fabricated by Emcore for 20 to 25 Gb/s operation, has a 7.5 µm aperture, sub-mA threshold, and 0.41 W/A slope efficiency. Two VCSELs are wirebonded to the transmitter chip, one outputting the optical signal and the other acting as a dummy load. The power consumption of the dummy VCSEL is not counted in the power efficiencies reported here since in a product design, the dummy load VCSEL would be straightforwardly replaced by an on-chip resistive load or omitted entirely to save power.
Fig. 1 (a) Optical link block diagram, (b) Feed-forward equalization waveform (from [4]). (c) Photograph of transmitter IC and VCSELs mounted on high-speed PCB, (d) Photograph of receiver IC and photodiode mounted on high-speed PCB.
The effect of separating and recombining the post-cursor and main cursor paths is shown in Fig. 1(b). An adjustable delay bias varies the delay time caused by the chain of amplifiers. This combined with the adjustable post and main cursor tap weight causes the FFE output to act as a summation of the input signal with a delayed and an inverted copy of itself as shown in Fig. 1(b). The output of the FFE caries the same information as the input in a waveform with peaked rising and falling edges and a reduced DC swing. This emphasizes the high frequency portion of the waveform and can lead to improvements in bandwidth restricted components such as the VCSEL, MMF, photodiode (PD), transimpedance amplifier (TIA), and limiting amplifier (LA) [8].
The block diagram of the receiver IC is shown in Fig. 1(a). The receiver takes a differential ac-coupled signal into a transimpedance amplifier followed by six Cherry-Hooper stages and a CML output buffer to drive ac-coupled 50 Ω off-chip loads. The receiver transimpedance gain is approximately 12 kΩ at nominal supply voltages. The photodiode is also fabricated by Emcore with a 25 µm diameter. Both the transmitter and receiver ICs are fabricated in IBM’s standard bulk 90 nm CMOS process.
3. Optical link measurement results
The transmitter IC and VCSELs are mounted on a custom high-speed printed circuit board and the receiver IC and photodiode are mounted on separate board for testing. The TX and RX assemblies are shown in Figs. 1(c) and 1(d), where it is clear that the area of both ICs are pad limited and the high-speed circuitry occupies a small fraction of the chip footprint. In the TX chip, the main and post-cursor amplifier stages are highlighted, with the equalizer circuitry occupying ~40% of the total circuit area. The transmitter and receiver are joined by 4 m (2 + 2 m lengths) of OM2 MMF using lensed 50 µm MMF probes to couple emission from the VCSEL and to focus onto the photodiode. The coupling efficiency on the TX side is ~80%, and close to 100% on the RX side. A 30 GHz bandwidth sampling oscilloscope is used for electrical receiver output eye diagram measurements and a 17 GHz bandwidth Newport D-25xr photodiode is used to capture transmitter optical eye diagrams.
The first measurements focus on finding the maximum data rate where the link could operate at a bit error rate (BER) < 10−12. A high-speed pattern generator ac-coupled to the transmitter provides the 27-1 PRBS differential electrical input data with an amplitude of ~500mV. The maximum attainable bit rate is found to be 30 Gb/s. The optical VCSEL output, electrical receiver output, and timing margin characteristics at 30 Gb/s are shown in Fig. 2. The receiver output and timing margin characteristics show a clear eye opening of 0.31 UI at a BER of 10−12. The VCSEL output shows that the optical waveform is over-equalized to compensate for bandwidth limitations of components in the receiver as well.
Fig. 2 30 Gb/s results: (a) Electrical receiver output, (b) Timing margin characteristics, (c) Optical VCSEL output.
Next, the link is optimized for power efficiency. 30 Gb/s represents the maximum bit rate achievable for this link and the maximum power consumption. At lower bit rates, power supplies can be turned down, which reduces the overall power consumption in exchange for bandwidth. At each data rate shown in Fig. 3, the power efficiency is optimized while maintaining a BER < 10−12 and a single-ended output amplitude greater than 100 mV peak-to-peak. In this measurement, the TX and RX are directly connected with no added attenuation: there is no optical margin in the link. A minimum power efficiency of 2.95 pJ/bit is found at 20 Gb/s, while the minimum absolute power consumption of 45.2 mW occurs at 10 Gb/s. Below 10 Gb/s, the link’s power consumption cannot be further optimized without violating the output amplitude restriction.
Table 1 shows the power consumption for the various supplies indicated in Fig. 1(a). The limiting amplifier consumes most of the power, and cannot be reduced at data rates below 20 Gb/s without sacrificing the receiver output amplitude. The link’s bandwidth limitations make it less efficient at higher bit rates since the supply voltages must be increased to gain more bandwidth. Nearly 150 mW must be added to increase from 20 Gb/s to 30 Gb/s, while only 14 mW is needed to increase from 10 Gb/s to 20 Gb/s. Figure 3 also shows the effect of equalization on power efficiency. The measurement procedure is the same as above; however, the link is optimized at each data rate with post-cursor DELAY and TAP grounded, disabling the equalization. Without equalization, the maximum achievable bit rate is 25 Gb/s and the best power efficiency is 3.48 pJ/bit at 18 Gb/s. At 14 Gb/s, the curves begin to converge indicating that the link is no longer bandwidth limited and there is no performance improvement with equalization enabled.
Table 1. Power consumption (mW) for supplies shown in Fig. 1.
To further characterize the link, nominal settings are chosen such that the equalized link can operate at 25 Gb/s with a BER < 10−12, output amplitude > 100 mV, and with 2 dB of link margin. The choice of 2 dB of margin is somewhat arbitrary, allowing a programmable optical attenuator to be inserted between the two OM2 fiber lengths to facilitate receiver sensitivity measurements, but also represents a realistic operating point since in practice optical interconnects are not operated with no margin. The power consumption is 127 mW with equalization and 115 mW without equalization. At the nominal settings without equalization, the maximum bit rate is 23.5 Gb/s with a BER < 10−12 and output amplitude > 100 mV.
Figures 4(a) and 4(b) show electrical receiver output eye diagrams for a range of data rates at nominal settings. There is a clear degradation in eye quality at 23.5 and 25 Gb/s without equalization. This degradation is quantified in Fig. 5, which indicates a 17% reduction in timing margin at 23.5 Gb/s without equalization. On the other hand, there is almost no reduction in timing margin at 22 Gb/s without equalization. This indicates that at 22 Gb/s the link is operating within its bandwidth limitations at the given nominal settings.
Fig. 4 (a) Electrical Rx output equalized (Vpp = 240 mV), (b) Electrical Rx output without equalization (Vpp = 240 mV), (c) Optical VCSEL output equalized (OMA = 0.82 mW), (d) Optical VCSEL output without equalization (OMA = 0.95 mW).
Fig. 5 (a) Timing margin characteristics at 22 Gb/s, (b) Timing margin characteristics at 23.5 Gb/s.
Figures 4(c) and 4(d) show the optical VCSEL output over the same range of bit rates at the nominal settings. As expected, the equalized link shows significant overshoot, undershoot, and reduced DC swing as a result of the waveform shaping shown in Fig. 1. The optical eye without equalization shows more closure with increasing data rates compared to the equalized eye, which speaks to the improvement on the VCSEL’s bandwidth resulting from equalization.
Figure 6 shows the receiver sensitivity for the link with and without equalization. With equalization, the receiver sensitivity shows 4 dB of link margin improvement at 23.5 Gb/s. At 20 Gb/s the improvement is 1 dB, and at 10 Gb/s there is no improvement. This matches the timing margin results at these nominal setting that showed significant bandwidth limitations at 23.5 Gb/s without equalization and less improvement at data rates below 22 Gb/s. Equalization offers substantial benefits in sensitivity and timing margin when operating near the link’s maximum bit rate; however, when operating within the link’s bandwidth capability, equalization does not produce significant improvements in these metrics.
Fig. 6 (a) Receiver sensitivity for the equalized link, (b) Comparison of receiver sensitivity with and without equalization.
4. Conclusion
In this paper, we demonstrated a VCSEL-based MMF optical link using 90 nm CMOS circuits that achieves a 30 Gb/s data rate, a record for CMOS-driven optical links. The link has a best power efficiency of 2.95 pJ/bit at 20 Gb/s. Equalization has been shown to provide dramatic improvements in maximum bit rate, power efficiency, receiver sensitivity, and timing margin. For a given power setting, equalization is most useful near the link’s maximum bit rate and is less helpful at lower speeds where the link is not bandwidth limited.
Acknowledgments
The authors would like to thank M. Taubenblatt for management support, and Sumitomo Electric Device Innovations USA (formerly Emcore) for the VCSELs and PDs. The authors gratefully acknowledge support from DARPA under contract MDA972-03-3-0004. The views, opinions, and/or findings contained in this article are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of DARPA or the Department of Defense. Approved for Public Release, Distribution Unlimited.
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