Universal method for constructing N-port non-blocking optical router based on 2 × 2 optical switch for photonic networks-on-chip

Qiaoshan Chen; Fanfan Zhang; Ruiqiang Ji; Lei Zhang; Lin Yang

doi:10.1364/OE.22.012614

1. Introduction

While manufacturing technology improves, the number of transistors on integrated circuits doubles approximately every two years and its speed becomes faster and faster [1]. The performance of processor has been steadily improved partly by improving the clock frequency and mainly by integrating more higher-performance processor cores on a chip. For chip multiprocessor (CMP), its performance is determined not only by the number of the processor cores integrated on a chip, but also by the communication efficiency among them. With CMP continuously requiring more communication bandwidth, metallic-based electrical network-on-chip (NoC) gradually becomes the bottleneck for improving the performance of CMP due to its high power consumption, limited bandwidth and long latency [2, 3]. Photonic NoC [4–6] is considered as a potential solution to overcome the limitations of its electrical counterpart [7, 8].

Lasers [9, 10], modulators [11–13], multiplexers/de-multiplexers [14–16] and detectors [17, 18] are the building blocks for the point-to-point optical interconnect. However, the processor core in CMP is required to be able to communicate with any other processor cores. This function is performed by the optical router, which is located at each node of photonic NoC and is responsible for connecting the local node with other nodes. Many topologies for photonic NoCs have been widely studied, such as Mesh [19], Cluster-Mesh, Torus [20], Crossbar [21], Fat-Tree [22] and Clos [23].

Different photonic NoCs require different optical routers. For example, Mesh photonic NoC shown in Fig. 1(a) requires 3-, 4- and 5-port optical routers, while Fat-Tree Photonic NoC shown in Fig. 1(c) only require 4-port optical router. Several 4- and 5-port optical routers based on microring (MR) optical switches or Mach-Zehnder (M-Z) optical switches have been proposed or even demonstrated [24–37]. Only 4- and 5-port optical routers are not enough to construct all photonic NoCs. High-radix non-blocking optical routers have potential applications in the future on-chip optical interconnects, such as Cluster-Mesh and Clos photonic NoCs. For example, the optical router used in Cluster-Mesh photonic NoC is dependent on the number of the processor cores located at each node and the Cluster-Mesh photonic NoC shown in Fig. 1(b) requires 8-port optical router. The optical router used in Clos photonic NoC is dependent on the scale of the network and the number of the processor cores located at each terminal node. The Clos photonic NoC shown in Fig. 1(d) requires 9-port optical router at the terminal node and 12-port optical router at the middle node. We also propose a general guideline for designing the N-port non-blocking optical router based on MR optical switches [31].

Fig. 1 (a) Mesh (b) Cluster-Mesh (c) Fat-Tree (d) Clos photonic networks-on-chip.

Download Full Size | PDF

Although MR optical switch or M-Z optical switch can manipulate two optical links simultaneously, most reported optical routers fully utilize them as 1 × 2 optical switches [25–32] or partly utilize them as 1 × 2 optical switches [24]. In this paper, we propose a universal method for constructing the N-port non-blocking optical router, in which all MR optical switches or M-Z optical switches behave as 2 × 2 optical switches. The optical router constructed by this method has minimum optical switches, in which the number of the optical switch is reduced about 50% compared to the reported optical routers based on MR optical switches [25–32] and more than 30% compared to the reported optical routers based on M-Z optical switches [24], and therefore is more compact in footprint and more power-efficient. By using passive-routing optical links [21], we can further reduce the power consumption of the optical router. We also present a strict mathematical proof of the non-blocking routing of the N-port optical router and the comparisons of the proposed optical routers with the reported optical routers.

The rest of this paper is organized as follows. In section 2, we introduce the properties of the 2 × 2 MR and M-Z optical switches. In section 3, we firstly introduce the basic rules for constructing the N-port non-blocking optical router. Secondly, we introduce the 3- and 4-port optical routers and demonstrate their non-blocking routing by exhausting all optical links in each routing state. Finally, we introduce the expanding method from the (N-2)-port non-blocking optical router to the N-port non-blocking optical router. In section 4, we present a mathematical proof of the non-blocking routing of the N-port optical router constructed by the proposed method. In section 5, we present the comparisons of the proposed optical routers with the reported optical routers. In section 6, we give a summary of this work.

2. 2 × 2 optical switch

Figures 2(a) and 2(b) show the schematics of the M-Z optical switch and the MR optical switch with. Note that the MR optical switch is arranged so that two input ports are located at one side and two output ports are located at the other side. All two optical switches can be abstracted as a simplified 2 × 2 optical switch and the details in the dotted box do not affect our discussion on the construction method.

Fig. 2 Schematic of (a) M-Z optical switches, (b) the MR optical switch.

Download Full Size | PDF

When the 2 × 2 optical switch is on the “bar” status, two incident lights will be guided from the input port I₁/I₂ to the output port O₁/O₂. While the 2 × 2 optical switch is on the “cross” status, two incident lights will be guided from the input port I₁/I₂ to the output port O₂/O₁.

The M-Z optical switch is capable of switching between the “bar” and “cross” statuses with nanosecond switching time, as reported previously [38–40]. And through the arm difference design, we can achieve that when no voltage applied to the device, the M-Z optical switch is on the “cross” status, and when the voltage applied to the device to achieve pi/2 phase difference between the two arms, the M-Z optical switch is on the “bar” status. This means that for such a kind of M-Z optical switch, it consumes no power when operating on the “cross” status. For the MR optical switch adopted by most optical routers in the literature, the MR is on-resonance at the working wavelength when no voltage is applied to the device. And the incident light will be directed to the drop-port of the MR, i.e. the MR optical switch is on the “bar” status. When a voltage with a certain amplitude applied to the MR, it will be tuned to be off-resonance at the working wavelength and the incident light will be directed to the through-port of the MR, i.e. the MR optical switch is on the “cross” status.

Generally, M-Z optical switch with two balanced arms has a much larger optical bandwidth due to its symmetric interference architecture, while MR optical switch has much lower power consumption due to the multi-beam interference in its ring cavity architecture. Since MR optical switch has a periodic filtering spectrum, it can manipulate the wavelength division multiplexing (WDM) optical signals with channel spacing equal to the MR’s free spectral range (FSR) [28]. Therefore the aggregate bandwidth of the optical router based on MR optical switches can be expanded through wavelength multiplexing. Since the FSR and radius of MR satisfy the relation of FSR = $λ 0^{2}$ /2πR⋅N_g, where $λ 0$ is the resonance wavelength of MR, 2πR is the perimeter of MR, and N_g is the group refractive index of waveguide. So, in order to multiplex WDM optical signals with more than 16 channels in the C-band, the radius of the MR should be enlarged to about 40 μm to achieve a channel spacing of 2.5 nm. The footprint of the MR optical switch will be comparable to that of the M-Z optical switch.

3. N-port non-blocking optical router

3.1. Basic rules for constructing N-port non-blocking optical router

Any N-port non-blocking optical router for photonic NoC must obey the following rules, which have been adopted in the reported optical routers [19–27]:

(1) Light injected into the input of any one port can be guided to the output of any other ports.
(2) Light injected into the input of any one port should not be guided to the output of the same port (no “U” turn exists) since the local communication in one processor core can be conveniently carried out by electrical interconnect. Such a characteristic makes the constructing method for the optical router is different from that for the optical switch [41].
(3) Any optical link between the input of one port and the output of another port would never block any possible optical links between the remaining input ports and output ports.

For an N-port non-blocking optical router, light injected into the input of one port must be able to be guided to any output of the remaining (N-1) ports. Therefore, there must be (N-1) optical links for any one port. If all the optical switches in the pair optical links between any two ports (denoted as I_i→O_j and I_j→O_i) are on the “cross” statuses, the optical signals can be passively routed between the two ports. Passive optical links can route optical signals with fixed wavelengths and do not require extra electrical control circuits, which tends to have better power performance. Therefore, a power-efficient optical router should use as many passive optical links as possible. For the specific port i, its N-1 optical links are designed as follows. As shown in Fig. 3(a), all optical switches in the optical links between port i (i is an odd number and ≥1) and port i + 1 are on the “cross” statuses. To establish any optical link between port i and any port of the remaining N-2 ports, only one optical switch is on the “bar” status and the remaining optical switches are on the “cross” statuses (as shown in red line in Fig. 3(b)). At least N-2 1 × 2 optical switches are needed to establish all the optical links between port i and the remaining N-2 ports (as shown in Fig. 3(c)). Therefore, the N-port non-blocking optical router based on 1 × 2 optical switch at least has N(N-2) optical switches if N is an even number. If N is an odd number, we firstly do not consider input port N and output port N. The (N-1)-port non-blocking optical router based on 1 × 2 optical switch at least needs (N-1)(N-3) optical switches. For input port N and output port N, 2(N-1) optical switches are required to establish the optical links between them and the remaining N-1input ports and N-1output ports. So, if N is an odd number, the N-port non-blocking optical router based on 1 × 2 optical switch at least has (N-1) × (N-3) + 2(N-1) = (N-1)² optical switches.

Fig. 3 (a) and (b) Specific optical links of the input port i based on 1 × 2 optical switches (c) N-1 optical links of the input port 1 based on 1 × 2 optical switches.

Download Full Size | PDF

Compared to 1 × 2 optical switch (see Fig. 4(a)), 2 × 2 optical switch manipulate two optical links simultaneously (see Fig. 4(b)). One 2 × 2 optical switch can realize the functions of two 1 × 2 optical switches. If the N-port non-blocking optical router is constructed by 2 × 2 optical switches, the number of the used optical switches can be reduced by half. Therefore at least N(N-2)/2 optical switches are required if N is an even number and at least (N-1)²/2 optical switches are required if N is an odd number. Since the number of the used optical switches is dependent on the parity of N, we firstly introduce the simplest two optical routers when N is an odd and even number, respectively, and then introduce the expanding method from the (N-2)-port non-blocking optical router to the N-port non-blocking optical router. It should be noted that the expanding method for the N-port non-blocking optical router does not depend on the parity of N although the start point is different when N is an odd or even number.

Fig. 4 (a) 1 × 2 optical switch and (b) 2 × 2 optical switch.

Download Full Size | PDF

3.2. 3- and 4-port optical routers

Table 1 shows the schematics of the 3- and 4-port optical routers and their routing tables. Note that the coding number is arranged from small to large for the input ports and from large to small for the output ports. For simplicity, the optical link from input port i to output port j is defined as I_i→O_j. Blocking occurs when one optical switch is on the “cross” status in one optical link while on the “bar” status in another optical link, while the two optical links should be established simultaneously in a specific routing state. The 3-port optical router has two routing states and the 4-port optical router has nine routing states. To demonstrate their non-blocking routing, all of the possible cases are listed in Table 2. Clearly, the 3- and 4-port optical routers are non-blocking and their optical links obey the aforementioned rules.

Table 1. Schematics of the 3- and 4-port Optical Routers and Their Routing Tables

View Table | View all tables in this article

Table 2. Comparison of the Proposed 4-port Optical Router with the Reported 4-port Optical Routers [24–27]

View Table | View all tables in this article

3.3. Expanding method from the (N-2)-port non-blocking optical router to the N-port non-blocking optical router

We have demonstrated that the 3- and 4-port optical routers are non-blocking in section 3.2. Based on them, we can construct the N-port non-blocking optical router by the expanding method. Figure 5 illustrates the expanding method from the (N-2)-port optical router to the N-port optical router. Two waveguides and 2(N-2) optical switches are added to the (N-2)-port optical router. The optical links between the N-2 original ports and the two new ports can be established by the added 2(N-2) optical switches as follows. The coding number is arranged from small to large for the input port and from large to small for the output port. Input port i of the N-port optical router is labeled as I_i and output port i of the N-port optical router is labeled as O_i. Output port i of the (N-2)-port optical router is labeled as I_i’ (i is an integer and 1≤i≤N-2). When the newly added optical switches $S_{1}^{T}$ , $S_{2}^{T}$ , …, $S_{N - 3}^{T}$ , $S_{N - 2}^{T}$ , $S_{1}^{D}$ , $S_{2}^{D}$ , …, $S_{N - 3}^{D}$ and $S_{N - 2}^{D}$ are on the “cross” statuses, the optical links I_i’→O_i, I_N-1→O_N and I_N→O_N-1 are established; when the optical switch $S_{i}^{T}$ is on the “bar” status, the optical link I_N-1→O_i is established; when the optical switch $S_{i}^{D}$ is on the “bar” status, the optical link I_N→O_i is established; when the optical switch $S_{i}^{T}$ is on the “bar” status, the optical link I_i’→O_N is established; when the optical switch $S_{i}^{D}$ is on the “bar” status, the optical link I_i’→O_N-1 is established. The N-port optical router constructed by this method is non-blocking and a strict mathematical proof will be shown in the next section.

Fig. 5 Expanding method from the (N-2)-port non-blocking optical router to the N-port non-blocking optical router.

Download Full Size | PDF

Following the expanding method, the 5-port optical router can be constructed by adding two waveguides and six optical switches (S₃, S₄, S₅, S₆, S₇, S₈) to the 3-port optical router and the 6-port optical router can be constructed by adding two waveguides and eight optical switches (S₅, S₆, S₇, S_8, S₉, S₁₀, S₁₁, S₁₂) to the 4-port optical router (see Figs. 6(a) and 6(b)). The 5- and 6-port optical routers have 8 and 12 optical switches respectively, which is about 50% less than the reported optical routers based on MR optical switches [28–32]. The 5-port optical router has 44 routing states and the 6-port optical router has 265 routing states. In order to check whether blocking occurs or not, we exhaust all optical links in each routing state and find that the 5- and 6-port optical routers are non-blocking.

Fig. 6 Schematics of the (a) 5-port and (b) 6-port non-blocking optical routers.

Download Full Size | PDF

4. Mathematical proof of the non-blocking routing of the N-port optical router

As previously mentioned, blocking occurs when one optical switch is on the “cross” status in one optical link while on the “bar” status in another optical link and these two optical links should be established simultaneously in a specific routing state. In section 3.2, we have demonstrated the non-blocking routing of the 3- and 4-port optical routers by exhausting all routing states and all optical links in each routing state. In section 3.3, we have presented the expanding method from the (N-2)-port non-blocking optical router to the N-port non-blocking optical router. When N is an odd number, the 5-, 7-,…, (N-2)- and N-port optical routers can be constructed successively based on the 3-port optical router by the expanding method. When N is an even number, 6-, 8-,…, (N-2)- and N-port optical routers can be constructed successively based on the 4-port optical router by the expanding method. So we can conveniently suppose that the (N-2)-port optical router is non-blocking since we have demonstrated that the 3- and 4-port optical routers are non-blocking by the method of exhaustion. If we can prove that the newly established ports can be communicated with the original ports and the newly established optical links will not block the original optical links, the non-blocking routing of the N-port optical router will be proved.

The method for proving the non-blocking routing of the N-port optical router is shown as follows. We firstly establish the fundamental relations between all input ports and all output ports by the recursive method and find that all optical links between all input ports and all output ports can be classified into seven types. By analyzing the characteristics of the seven types of optical links, we find that blocking possibly occurs only in three cases. By further analyzing the three possible blocking cases, we find that they do not obey the fundamental rules of the optical router and thus do not occur in reality.

When the optical switch S_i (1≤i≤N-2) is on the “cross” status, the status of the optical switch is defined as $\bar{S i}$ . When the optical switch S_i is on the “bar” status, the status of the optical switch is defined as S_i. We consider 2(N-2) optical switches as a structure cascaded by N-2 expanding elements (as shown in Fig. 7).

Fig. 7 Expanding switching structure composed of cascaded (N-2) expanding elements.

Download Full Size | PDF

We define the two optical switches in the i-stage expanding element as $S_{i}^{T}$ and $S_{i}^{D}$ . The input and output ports of the i-stage expanding element are donated as I_i’, $I_{i}^{T}$ , $I_{i}^{D}$ and $O_{i}$ , $O_{i}^{T}$ , $O_{i}^{D}$ . The input-output function of the i-stage expanding element can be simply calculated by Eqs. (1)-(7).

O_{i} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot \bar{S_{i}^{D}}

O_{i} = I_{i}^{D} \cdot S_{i}^{D}

O_{i} = I_{i}^{T} \cdot S_{i}^{T} \cdot \bar{S_{i}^{D}}

O_{i}^{T} = I_{i}^{T} \cdot \bar{S_{i}^{T}}

O_{i}^{T} = I_{i}^{'} \cdot S_{i}^{T}

O_{i}^{D} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot S_{i}^{D}

O_{i}^{D} = I_{i}^{D} \cdot \bar{S_{i}^{D}}

when the i-stage expanding element is cascaded to the (i + 1)-stage expanding element (see Fig. 8), their relationship satisfies Eqs. (8) and (9):

I_{i + 1}^{T} = O_{i}^{T}

I_{i + 1}^{D} = O_{i}^{D}

According to Eqs. (1)-(9), we can obtain the input-output function of the N-port optical router by the recursive method.

Fig. 8 Relationship between the i-stage expanding element and the (i + 1)-stage expanding element.

Download Full Size | PDF

O_{i} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot \bar{S_{i}^{D}}

O_{i} = I_{N - 1} \cdot \bar{S_{1}^{T}} \cdot \bar{S_{2}^{T}} \cdot \cdot \cdot \bar{S_{i - 1}^{T}} \cdot S_{i}^{T} \cdot \bar{S_{i}^{D}}

O_{i} = I_{N} \cdot \bar{S_{1}^{D}} \cdot \bar{S_{2}^{D}} \cdot \cdot \cdot \bar{S_{i - 1}^{D}} \cdot S_{i}^{D}

O_{N - 1} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot S_{i}^{D} \cdot \bar{S_{i + 1}^{D}} \cdot \cdot \cdot \bar{S_{N - 2}^{D}}

O_{N - 1} = I_{N} \cdot \bar{S_{1}^{D}} \cdot \bar{S_{2}^{D}} \cdot \cdot \cdot \bar{S_{i}^{D}} \cdot \cdot \cdot \bar{S_{N - 2}^{D}}

O_{N} = I_{i}^{'} \cdot S_{i}^{T} \cdot \bar{S_{i + 1}^{T}} \cdot \cdot \cdot \bar{S_{N - 2}^{T}}

O_{N} = I_{N - 1} \cdot \bar{S_{1}^{T}} \cdot \bar{S_{2}^{T}} \cdot \cdot \cdot \bar{S_{i}^{T}} \cdot \cdot \cdot \bar{S_{N - 2}^{T}}

Blocking occurs when one optical switch is on the “cross” status in one optical link and on the “bar” status in another optical link and the two optical links should be established simultaneously in one specific routing state. So we can prove the non-blocking routing by reduction to absurdity. In the seven types of optical links, there are only three cases in which blocking possibly occur.

Blocking case I

\begin{matrix} O_{i} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot \bar{S_{i}^{D}} & (10) \\ (a) \\ O_{i} = I_{N - 1} \cdot \bar{S_{1}^{T}} \cdot \bar{S_{2}^{T}} \cdot \cdot \cdot \bar{S_{i - 1}^{T}} \cdot S_{i}^{T} \cdot \bar{S_{i}^{D}} & (11) \end{matrix}

(b) \begin{matrix} O_{i} = I_{N - 1} \cdot \bar{S_{1}^{T}} \cdot \bar{S_{2}^{T}} \cdot \cdot \cdot \bar{S_{i - 1}^{T}} \cdot S_{i}^{T} \cdot \bar{S_{i}^{D}} \\ O_{i} = I_{N} \cdot \bar{S_{1}^{D}} \cdot \bar{S_{2}^{D}} \cdot \cdot \cdot \bar{S_{i - 1}^{D}} \cdot S_{i}^{D} \end{matrix} \begin{matrix} (11) \\ (12) \end{matrix}

Cases (a) and (d) show that the same optical switch $S_{i}^{T}$ has two different statuses in two optical links (I_i’→O_i, I_N-1→O_i; I_i’→O_N, I_N-1→O_N). If this situation happens, the lights injected into the two input ports I_i’ and I_N-1 will be directed to the same output port O_i or O_N. Based on the aforementioned three rules for the optical router, this situation will not occur in reality.

Case (b) shows that the same optical switch $S_{i}^{D}$ has two different statuses in two optical links (I_N-1→O_i, I_N→O_i). If this situation happens, the lights injected into the two input ports I_N-1 and I_N will be directed to the same output port O_i. Based on the aforementioned three rules for the optical router, this situation will not occur in reality.

Case (c) shows that the same optical switch $S_{i}^{D}$ has two different statuses in two optical links (I_i’→O_N-1, I_N→O_N-1). If this situation happens, the lights injected into the two input ports I_i and I_N will be directed to the same output port O_N_-1. Based on the aforementioned three rules for the optical router, this situation will not occur in reality.

Blocking case II

\begin{matrix} O_{N - 1} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot S_{i}^{D} \cdot \bar{S_{i + 1}^{D}} \cdot \cdot \cdot \bar{S_{N - 2}^{D}} & (13) \\ (a) \\ O_{N} = I_{i}^{'} \cdot S_{i}^{T} \cdot \bar{S_{i + 1}^{T}} \cdot \cdot \cdot \bar{S_{N - 2}^{T}} & (15) \end{matrix}

Cases (a) and (b) show that the same optical switch $S_{i}^{T}$ has two different statuses in two optical links (I_i’→O_N-1, I_i’→O_N ; I_N-1→O_i, I_N-1→O_N). If this situation happens, the light injected into the same input ports I_i’ or I_N-1 will be directed to the two output ports O_N-1 and O_N or O_i and O_N. Based on the aforementioned three rules for the optical router, this situation will not occur in reality.

Case (c) shows that the same optical switch $S_{i}^{D}$ has two different statuses in two optical links I_N →O_i and I_N →O_N-1. If this situation happens, the light injected into the same input port I_N will be directed to the two output ports O_i and O_N-1. Based on the aforementioned three rules for the optical router, this situation will not occur in reality.

Blocking case III

\begin{matrix} O_{i} = I_{N - 1} \cdot \bar{S_{1}^{T}} \cdot \bar{S_{2}^{T}} \cdot \cdot \cdot \bar{S_{i - 1}^{T}} \cdot S_{i}^{T} \cdot \bar{S_{i}^{D}} & (11) \\ O_{N - 1} = I_{i}^{'} \cdot \bar{S_{i}^{T}} \cdot S_{i}^{D} \cdot \bar{S_{i + 1}^{D}} \cdot \cdot \cdot \bar{S_{N - 2}^{D}} & (13) \end{matrix}

In this case, Eqs. (11) and (13) show that the optical switches $S_{i}^{T}$ and $S_{i}^{D}$ have two different statuses in two optical links I_N-1→O_i and I_i’→O_N-1. As aforementioned, when all the newly added optical switches are on the “cross” statuses, the optical links I_i’→O_i and I_N-1→O_N (i is an integer and 1≤i≤N-2) are established. When the optical link I_N-1→O_i is established as Eq. (11), the input port I_i’ cannot be communicated with the output port O_i and the input I_i’ should be idle. On the meanwhile, I_N-1 cannot be communicated with the output port O_N and the output port O_N should be idle. When the optical link I_i’→O_N-1 is established as Eq. (13) simultaneously, the input port I_N cannot be communicated with the output port O_N-1 and the input port I_N should be idle. According to the aforementioned rules, light injected into the input of any one port should not be guided to the output of the same port. So, the number of effective ports will be N-1, which means that the N-port optical router is used as a (N-1)-port optical router. As the method for constructing the N-port non-blocking optical router is dependent on the parity of N, this type of the optical links as shown in blocking case III should be established in the (N-1)-port optical router. This blocking case will not occur in reality.

Since all three possible blocking cases do not occur in reality, the proposed N-port optical router is non-blocking. For clarity, all input ports are arranged on one side of the N-port optical router and all output ports are arranged on the other side of the N-port optical router. In the actual application, the input and output for one specific port of the N-port optical router should be arranged in the same physical address to facilitate the construction of the photonic NoC, as shown in the reported optical routers [25–32]. Therefore the topology of the N-port optical router should be further optimized. Principally, only N optical waveguide crosses are introduced to the N-port optical router in this application. Figures 9(a) and 9(b) show the optimized architectures of the 3- and 4-port optical routers, in which only 3 and 4 waveguide crosses are added respectively. Although the proposed N-port optical router is designed for photonic NoCs, it also can be utilized for chip-to-chip, rack-to-rack optical interconnects and other optical communication systems adopting bidirectional communication mode.

Fig. 9 Schematics of the (a) 3-port and (b) 4-port non-blocking optical routers, in which the input and output for one specific port are arranged in the same physical address.

Download Full Size | PDF

5. Comparisons with other reported optical routers

The number of the optical links of the N-port non-blocking optical router $g (N)$ can be expressed as Eq. (17).

g (N) = N (N - 1)

For an N-port non-blocking optical router, one-to-one correspondences exist between its N input ports and N output ports. We define N input ports as a set In{1,2,……,N}, N output ports as a set Out{1,2,……,N}. We randomly rearrange the order of the N elements in the set Out. There are N! permutations of the set Out{1,2,……,N}. Therefore, there are totally N! routing states and each routing state comprises N independent links. We find that some U-turn cases exist in N! routing states, which are not necessary for the N-port non-blocking optical router. By analyzing the routing table of the N-port non-blocking optical router, we find that the total number of only one U-turn case occurring is $C_{N}^{1} f (N - 1) = C_{N}^{N - 1} f (N - 1)$ , the total number of only two U-turn cases occurring is $C_{N}^{2} f (N - 2) = C_{N}^{N - 2} f (N - 2)$ , …, and the total number of only N U-turn cases occurring is $C_{N}^{N} f (0) = C_{N}^{0} f (0)$ . Therefore, by removing the number of the routing states in which U-turn cases occur, the number of the routing states of the N-port non-blocking optical router $f (N)$ can be expressed as Eq. (18).

f (0) = 1, f (N) = N! - [C_{N}^{0} f (0) + C_{N}^{1} f (1) + C_{N}^{2} f (2) + \dots + C_{N}^{N - 1} f (N - 1)] = N! - \sum_{k = 0}^{N - 1} C_{N}^{k} f (k)

Where N is an integer and N≥1, k is an integer and 1≤k≤N-1. The coefficient

C_{N}^{k}

can be expressed as Eq. (19).

C_{N}^{0} = 1, C_{N}^{k} = \frac{N!}{(N - k)! k!}

Based on Eq. (18), the 3-, 4-, 5- and 6-port non-blocking optical routers have 2, 9, 44 and 265 routing states, which have been proved by counting the routing states directly from their routing tables.

Since all input ports are arranged on one side and all output ports are arranged on the other side for the reported optical router based on M-Z optical switch [24], we can compare the proposed optical router with it directly. Since the input and output for one specific port of the reported optical routers based on MR optical switches are arranged in the same physical address [25–31], we replace all 2 × 2 optical switches in the proposed optical routers by MR optical switches and arrange their input and output for one specific port in the same physical address. To facilitate expression, we define the propagation losses of the 2 × 2 optical switch on the “cross” and “bar” statuses as X_c and X_b respectively, the propagation loss of the waveguide cross as Y, the tuning power consumption of a 2 × 2 optical switch as P. Tables 2 and 3 show the comparisons of the proposed 4- and 5-port optical routers with the reported 4- and 5-port optical routers.

Table 3. Comparison of the Proposed 5-port Optical Router with the Reported 5-port Optical Routers [28–31]

View Table | View all tables in this article

The 4- and 5-port optical routers constructed by this method use 4 and 8 optical switches respectively, which is about 50% less than the reported optical routers based on MR optical switches [25–31] and more than 30% less than the reported optical router based on M-Z optical switches [24]. The number of the optical switches used by an optical router decides its footprint and the complexity of its layout. Therefore, the proposed optical routers are more compact in footprint and less complex in layout than the reported optical routers [24–31].

Power consumption is one critical point for designing photonic NoC. To establish different optical links will require different power consumption for the optical routers. To characterize the power efficiency of the optical routers, we get the average power consumption per routing state by the statistics method. We assume that each routing state occurs with equal probability. Based on Eq. (18), 4-port optical router has 9 routing states, each of which comprises 4 independent links, and 5-port optical router has 44 routing states, each of which comprises 5 independent links. As shown in Tables 2 and 3, the average power consumption of the proposed 4-port optical router is at least 20% less than the reported 4-port optical routers [24–27] and the average power consumption of the proposed 5-port optical router is at least 28% less than the reported 5-port optical routers [28–31].

Insertion loss is another critical point for designing photonic NoC. Different optical links of an optical router may have different insertion losses. Best-case loss is the smallest insertion loss of all optical links of the optical router. Worst-case loss is the largest insertion loss of all optical links of the optical router. Average loss is the average insertion loss of all optical links of the optical router with the assumption that each optical link occurs with equal probability. The 4-port optical router has 12 optical links and the 5-port optical router has 20 optical links. Tables 2 and 3 show the comparisons in best-case insertion loss, average insertion loss and worst-case insertion loss between the proposed 4- and 5-port optical routers and the reported 4- and 5-port optical routers [24–31]. We find that all optical routers have small difference in best-case insertion loss, average insertion loss and worst-case insertion loss.

Based on the above analysis, we can conclude that fully adopting 2 × 2 optical switches in the optical router can reduce its average power consumption and footprint without the sacrifice of its insertion loss.

6. Conclusion

We propose a universal method for constructing N-port non-blocking optical router for photonic networks-on-chip, in which all MR optical switches or M-Z optical switches behave as 2 × 2 optical switch. The optical router constructed by this method has the lowest power consumption and requires the least optical switches, in which the number of the optical switches is reduced about 50% compared to the reported optical routers based on MR optical switches and more than 30% compared to the reported optical routers based on M-Z optical switches, and therefore is more compact in footprint. We also present a strict mathematical proof of the non-blocking routing of the proposed N-port optical router and the insertion loss comparisons of the proposed optical routers with the reported optical routers.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (NSFC) under grants 61204061, 61235001, and 61377067, the National High Technology Research and Development Program of China under grants 2012AA012202 and 2013AA014203 and the Scientific and Technological Innovation Cross Team of Chinese Academy of Sciences.

References and links

1. R. Beausoleil, J. Ahn, N. Binkert, A. Davis, D. Fattal, M. Fiorentino, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “A nanophotonic interconnect for high-performance many-core computation,” in Proceedings of Integrated Photonics and Nanophotonics Research and Applications (Optical Society of America, 2008), paper ITuD2.

2. M. Briere, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Mieyeville, F. Gaffiot, and I. O. Connor, “System level assessment of an photonics NoC in an MPSoC platform,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (2007), pp. 1–6.

3. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” in Proceedings of the IEEE,97(7), pp. 1166–1185. [CrossRef]

4. A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” in Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (IEEE Computer Society, Washington, DC, 2009), pp. 124–133. [CrossRef]

5. M. K. Hung, Y. Yaoyao, W. Xiaowen, Z. Wei, L. Weichen, and X. Jiang, “A hierarchical hybrid optical-electronic network-on-chip,” in Proceedings of the IEEE Annual Symposium on VLSI, (IEEE Computer Society,Lixouri Kefalonia,2010), pp. 327–332.

6. M. Haurylau, G. Chen, H. Chen, J. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, “On-chip optical interconnect roadmap: challenges and critical directions,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1699–1705 (2006). [CrossRef]

7. T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects [Invited],” J.Opt. Netw. 6(1), 63–73 (2007). [CrossRef]

8. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” IEEE Micro 29(4), 8–21 (2009). [CrossRef]

9. A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “Electrically pumped hybrid AlGaInAs-silicon evanescent laser,” Opt. Express 14(20), 9203–9210 (2006). [CrossRef] [PubMed]

10. R. E. Camacho-Aguilera, Y. Cai, N. Patel, J. T. Bessette, M. Romagnoli, L. C. Kimerling, and J. Michel, “An electrically pumped germanium laser,” Opt. Express 20(10), 11316–11320 (2012). [CrossRef] [PubMed]

11. A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia, “A high-speed silicon optical modulator based on a metal-oxide-semiconductor capacitor,” Nature 427(6975), 615–618 (2004). [CrossRef] [PubMed]

12. G. Li, X. Zheng, J. Yao, H. Thacker, I. Shubin, Y. Luo, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning,” Opt. Express 19(21), 20435–20443 (2011). [CrossRef] [PubMed]

13. J. F. Ding, H. T. Chen, L. Yang, L. Zhang, R. Q. Ji, Y. H. Tian, W. W. Zhu, Y. Y. Lu, P. Zhou, R. Min, and M. B. Yu, “Ultra-low-power carrier-depletion Mach-Zehnder silicon optical modulator,” Opt. Express 20(7), 7081–7087 (2012). [CrossRef] [PubMed]

14. M. M. Geng, L. X. Jia, L. Zhang, L. Yang, P. Chen, T. Wang, and Y. L. Liu, “Four-channel reconfigurable optical add-drop multiplexer based on photonic wire waveguide,” Opt. Express 17(7), 5502–5516 (2009). [CrossRef] [PubMed]

15. P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010). [CrossRef] [PubMed]

16. J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008). [CrossRef]

17. J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonics 4(8), 527–534 (2010). [CrossRef]

18. S. Assefa, F. N. Xia, and Y. A. Vlasov, “Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects,” Nature 464(7285), 80–84 (2010). [CrossRef] [PubMed]

19. H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009). [CrossRef]

20. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008). [CrossRef]

21. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008. [CrossRef]

22. H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor systemon-chip,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (2009), pp. 3–8.

23. A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009). [CrossRef]

24. M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4x4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011). [CrossRef] [PubMed]

25. N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4x4 hitless slicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008). [CrossRef] [PubMed]

26. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011). [CrossRef] [PubMed]

27. Y. Ye, X. Wu, J. Xu, W. Zhang, M. Nikdast, and X. Wang, “Holistic Comparison of Optical Routers for Chip Multiprocessors,” in Anti-Counterfeiting, Security and Identification (ASID) International Conference, 1–5 (2012). [CrossRef]

28. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Five-port optical router for photonic networks-on-chip,” Opt. Express 19(21), 20258–20268 (2011). [CrossRef] [PubMed]

29. H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” Proc. IEEE Comput. Soc. Annu. Symp. 19–24(2009). [CrossRef]

30. A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009). [CrossRef]

31. R. Min, R. Ji, Q. Chen, L. Zhang, and L. Yang, “A universal method for constructing N-port nonblocking optical router for photonic networks-on- chip,” J. Lightwave Technol. 30(23), 3736–3741 (2012). [CrossRef]

32. R. Ji, J. Xu, and L. Yang, “Five-Port Optical Router Based on Microring and Switches for Photonic Networks-on-Chip,” IEEE Photon. Technol. Lett. 25(5), 492–495 (2013). [CrossRef]

33. T. Hu, H. Qiu, P. Yu, C. Qiu, W. Wang, X. Jiang, M. Yang, and J. Yang, “Wavelength-selective 4 × 4 nonblocking silicon optical router for networks-on-chip,” Opt. Lett. 36(23), 4710–4712 (2011). [CrossRef] [PubMed]

34. X. Tan, M. Yang, L. Zhang, Y. Jiang, and J. Yang, “A Generic Optical Router Design for Photonic Network-on-Chips,” J. Lightwave Technol. 30(3), 368–376 (2012). [CrossRef]

35. L. Zhou, S. S. Djordjevic, R. Proietti, D. Ding, S. J. B. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys., A Mater. Sci. Process. 95(4), 1111–1118 (2009). [CrossRef]

36. A. Kaźmierczak, W. Bogaerts, E. Drouard, F. Dortu, P. Rojo-Romeo, F. Gaffiot, D. Van Thourhout, and D. Giannone, “Highly integrated optical 4×4 crossbar in silicon-on-insulator technology,” J. Lightwave Technol. 27(16), 3317–3323 (2009). [CrossRef]

37. T. Hu, H. Shao, L. Yang, C. Xu, M. Yang, H. Yu, X. Jiang, and J. Yang, “Four-port silicon multi-wavelength optical router for photonic networks-on-chip,” IEEE Photon. Technol. Lett. 25(23), 2281–2284 (2013). [CrossRef]

38. W. M. J. Green, M. J. Rooks, L. Sekaric, and Y. A. Vlasov, “Ultra-compact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator,” Opt. Express 15(25), 17106–17113 (2007). [CrossRef] [PubMed]

39. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005). [CrossRef] [PubMed]

40. J. Van Campenhout, W. M. J. Green, S. Assefa, and Y. A. Vlasov, “Low-power, 2 x 2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks,” Opt. Express 17(26), 24020–24029 (2009). [CrossRef] [PubMed]

41. A. W. Poon, F. Xu, and X. Luo, “Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip,” Proc. SPIE 6898, 689812 (2008). [CrossRef]