1. Introduction

Digital coherent transmission is now widely used in long-reach networks, and its application field is now extending to shorter-reach metro networks, in which smaller transmission equipment along with reduced power consumption is strongly required. A discussion of coherent pluggable transceivers, including the centum form factor pluggable (CFP) and CFP2 types, has started in this context, and CFP2-type coherent transceivers will not be equipped with digital signal processors (DSP) inside the form factors, where reducing the size of optical receivers and transmitters is the key.

To further reduce receiver size while maintaining performance, photonic integration technologies, including hybrid, heterogeneous, and monolithic integration, have been intensively investigated as regards optical components [1–3]. However, a remaining problem is the dense integration of transimpedance amplifier (TIA)-ICs in electrical components. Conventional integrated coherent receivers (ICRs), defined by the OIF (Optical Internetworking Forum) implementation agreement as type 1 and type 2 [4], which are considered to be the foundation of the multi-source agreement (MSA), employ two dual-channel TIA-ICs with analog interfaces. In such a receiver, a bottleneck still exists in reducing the number of DC pins and the mounting area in the ICR. In addition, the DSP will not be mounted in CFP2-type transceivers and beyond, and this leads to additional technical issues related to large high-frequency loss caused by PCB boards and the RF connector between the receiver and DSP. A pre-emphasis function is desirable in order to compensate for such additional high-frequency loss. Therefore, a quad-channel TIA-IC with a serial peripheral interface (SPI) and a pre-emphasis function is promising for realizing an ultra-compact ICR.

In this paper, an ultra-compact ICR with a volume of 1.3 cc, which uses a quad-channel TIA-IC with a serial interface for pluggable transceivers, is demonstrated for the first time. Photodiode (PD) bias circuits are integrated in the TIA-IC, and shunt capacitors are used to minimize capacitor size. The bit-error-rate (BER) performance of the fabricated ICR has no penalty compared with conventional OIF-compliant receiver despite its high-density integration and SPI operation.

2. Design and fabrication of coherent receiver

Figure 1 is a schematic showing the size reduction achieved by using the newly developed quad-channel TIA IC. Quad-channel integration and the inclusion of the RC filter circuit within the TIA-IC reduce the mounting area of the electronic components. A serial interface is also effective in reducing the number of DC pins, which require space for fixing them on a printed circuit board. Additional functions can also be introduced by using a serial interface without increasing the module size or number of DC pins. Figure 2 shows a photograph of our fabricated ICR and two conventional ICRs. The new ICR comprises a monolithic octal-PD, a quad-channel TIA-IC, a miniaturized dual polarization optical hybrid (DPOH), and an ultra- compact ceramic package. Two separate polyimide-based flexible-printed circuits (FPCs) are attached at the rear of the package as low frequency (LF)/DC and RF electrical interfaces [5].

 

Fig. 1 Schematic comparing conventional ICR with dual-channel TIA-IC and ICR with quad-channel TIA-IC.

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Fig. 2 Photograph of coherent receivers.

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Two supply voltages and five SPI buses of serial clock, master in slave out, master out slave in, slave select, and reset, are printed on an LF/DC FPC, while four RF differential signals are designed on an RF FPC. The size of the coherent receiver is 7.7 × 30 × 5.8 mm³, excluding the FPCs, which is sufficiently small for even a CFP4 transceiver (21.5 × 89 × 9.5 mm³).

A block diagram of the quad-channel TIA-IC is shown in Fig. 3(a). It comprises four channels of differential TIAs with auto gain control (AGC) circuits and PD bias circuits, and SPI circuits with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). All the control functions, such as operation mode switching between AGC and manual gain control (MGC) as well as a monitoring function, can be accessed via the SPI. In addition, a frequency response control function that can individually control the bandwidth and magnitude of peaking, a bias circuit, and a current monitoring function for each PD are introduced. Such additional functions are also controlled by using an SPI. PD bias circuits comprise RC filters, circuits for photocurrent measurement, and 2 × 2 switches, which are connected to external PD voltage Vpd and internal variable supply voltage. The variable supply voltage is used to effectively deactivate each PD by biasing it in a positive bias region to measure interchannel crosstalk.

 

Fig. 3 (a) Block diagram, (b) photograph of TIA-IC and (c) schematic showing the effect of shunt capacitor.

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All the control functions and monitoring functions can be accessed via the SPI, which enables us to eliminate 31 DC pins out of 40 DC pins, which include 16 conventional analog interfaces (two operation mode switches, two shutdown switches, four peak detect monitors, four amplitude controls and four gain controls), seven PD supply voltages, and eight extra DC analog interfaces (four bandwidth controls and four peaking controls) in the ICR.

A photograph of the fabricated TIA-IC chip is shown in Fig. 3(b). We employed IBM 0.13-μm SiGe BiCMOS 8HP process for fabrication of the IC. The TIA-IC has differential input bias-signal-signal-bias (BSSB) and output ground-signal-signal-ground (GSSG) configurations for each channel, where bias B indicates the PD bias voltage. The chip size is 1.7 × 2.7 mm². Since the quad-channel chip size is almost doubled compared with conventional analog dual-channel IC, there is no significant size penalty as a result of the integration of the quad-channel and SPI.

Measured maximum transimpedance, bandwidth and dynamic range of the IC are 9.5 kΩ, 24 GHz, and 41 dB, respectively. Input referred current density is 24 pA/rtHz, and THD is only 1.2% at 500 mVpp differential output swing and 0.7 mApp differential input signal condition. Power consumption is 1.4 W.

When there is large frequency loss expected with pluggable transceivers and an ICR pre-emphasis function is used, output swing at the ICR output decreases as electric signal is transmitted through the PCB, since the peak-frequency component, which determines the output swing, attenuates at PCB. The developed IC produces 1300 mVppd at a −20 dBm input signal and 13 dBm local signal condition and thus has a 5-dB margin with respect to the OIF-standardized maximum output swing of 700 mVppd.

To minimize the mounting area of electronic components, bias voltages are supplied from the TIA IC to a PD chip via a PD chip-on-carrier (CoC) and RC filters are integrated in the TIA-IC, instead of using external components in conventional receivers [6,7]. To suppress high-frequency component on the bias lines, cathodes of dual PDs in each channel are shunted with a 3.5 pF on-chip capacitor. By using such a configuration, the value of the capacitor can be reduced to one-fourth of the total capacitance when an input signal is differential, compared with when two independent capacitors are connected between PD cathodes and ground. This is because the latter configuration is equivalent to two serially connected capacitors for a differential input signal. Effect of shunt capacitor is schematically depicted in Fig. 3(c). With the capacitor, differential high frequency component on the PD bias line cancels and high-frequency signal transmits only on the signal line. Without the capacitor, high-frequency signal generated by the photodiode transmits not only on signal lines but also on unterminated PD bias lines, which reflects in TIA and deteriorates group delay variation. Series resistors are also inserted at the cathode of each PD to suppress resonance involving shunt capacitors and bonding wires between the CoC and TIA-IC chip. Moreover, because of the shunt configuration, ground pads are not necessary on the PD and no DC voltage is applied across the shunt capacitors. As a result, a monolithically integrated octal version of InGaAs/InP PD [8] with the pitch of 250 μm is newly designed with the shunt capacitors.

The PLC-based DPOH, which integrates beam splitters and optical hybrids, was designed and fabricated with a chip size of 4 × 17 mm² using waveguides with a high index contrast of Δ = 1.5% [9], which is very promising for realizing compact coherent receivers while maintaining excellent optical performance.

The optical coupling system between the DPOH and PD array is an octal-PD extension of our previous device [6], in which two quad-PDs are independently coupled with a DPOH. The optical signal output from the DPOH is launched into the PD chip, which is mounted on the vertical surface of a ceramic CoC. Four channel differential BSSB transmission lines were designed and patterned on two sides of the CoC, which converts vertical transmission lines to horizontal ones. Such a configuration enabled the use of a single lens, a short distance of only a few hundred micrometers between the DPOH and PD array, and stable optical coupling.

In fabricating the coherent receiver, PD/CoC and a micro-lens array are aligned and fixed with the PLC subassembly, which comprises a PLC and a pigtailed fiber. Then, the PLC subassembly, TIA-IC, and other components, such as IC carriers or bypass capacitors, are mounted in a ceramic package and electronically connected by wire-bonding.

3. Group delay deviation and interchannel crosstalk

To verify the improvement of crosstalk and group delay deviation with bias capacitors integrated in the PD array, we analyzed the change of crosstalk and group delay of the coherent receiver by simulation and measurement.

Figures 4(a) and 4(b) compare group delay performance with and without bias capacitors. Simulation was performed with the measured S parameter of the TIA-IC, a coupled transmission line model which models the CoC, and a small signal model of the PD on Agilent ADS. Simulated group delay is calculated from the phase change of the simulated output obtained by the AC analyses. Bandwidth and group delay was measured by constructing an interferometer and using a lightwave component analyzer [10]. The 6-dB and 3-dB bandwidth of the ICR including the FPC leads were 22 and 17 GHz, respectively. In Figs. 4(a) and 4(b), reduction of group delay deviation is confirmed both in the simulation and measurement. Group delay deviation within 6-dB bandwidth of 22 GHz is reduced from 100 to 44 ps. The agreement between the measurement and simulation ensures that the group delay deviation is suppressed solely by the shunt capacitors.

 

Fig. 4 (a) Measured and (b) simulated group delay of the group delay of coherent receiver.

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Figures 5(a) and 5(b) show the results of interchannel crosstalk. When only the third channel input is activated, relative crosstalk in these graphs is obtained as the ratio of second channel output with respect to the third through channel output. We can see that crosstalk is much reduced and is less than −25 dB below 22 GHz with the shunt capacitors.

 

Fig. 5 Relative interchannel crosstalk of receiver (a) with and (b) without shunt capacitors.

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4. Transmission measurement results

To evaluate the transmission performance of the receiver, we measured dependence of the Q-value on the optical signal-to-noise ratio (OSNR). Supply bias voltage of both the PD and TIA-IC is 3.3 V. The measurement setup is shown in Fig. 6(a). To generate a 128-Gbit/s DP-QPSK signal, a 1550-nm tunable laser signal was modulated using a lithium niobate modulator. ASE noise was added to the optical signal to control the OSNR, and the signal was launched into the ICR. The signal power was set at −10 dBm. A 13-dBm integrated tunable laser assembly was used to provide a local oscillator signal for intradyne signal reception. The measurements of the ICR and conventional ICR (Type-1 form factor) with dual-channel TIA- ICs were performed under the same conditions. The Q value was calculated using a commercial modulation analyzer.

 

Fig. 6 (a) Measurement setup (b) OSNR dependence (at signal power of −10 dBm) and (c) signal-power dependence (at OSNR of 15.5 dB) of Q value.

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The OSNR dependence and signal power dependence of the Q value is shown in Fig. 6(b) and 6(c), respectively. In these graphs, the transmission performance of the ICR is equivalent to that of a conventional ICR, which means that there was no penalty caused by the integration of an SPI or by crosstalk, accompanying quad-channel integration. We also obtained a clear constellation diagram in the inset to Fig. 6(b). 6-dB and 3-dB bandwidth of the conventional ICR were 22 and 20 GHz, respectively.

While register values are stored and when there is no reading or writing operation via the SPI, clock signal is not supplied to the TIA-IC. To investigate whether transmission performance is affected by SPI operation, we measured the Q value while continuously accessing the SPI. The decrease in the Q value was less than 0.1 dB and was within measurement error, in spite of the provided 6-MHz 3.3-V_pp SPI clock signal.

5. Summary

We demonstrated an ultra-compact ICR with the volume of 1.3 cc using a quad channel TIA-IC with a serial interface for the first time. Compact implementation was realized by the use of a quad-channel TIA-IC with a serial interface and PD bias circuits, a miniature DPOH, and small optical coupling system. PD bias capacitors are shown to be effective for suppressing crosstalk between channels and group delay deviation for each channel, and a shunt configuration is introduced to minimize the capacitance value.

The ICR exhibits sufficient transmission performance for long-haul applications, which means that there is no Q-penalty from the existing conventional OIF-compliant receiver with an MSA package, despite its high-density integration and the continuous operation of a serial interface.