Open Access
Add to BibSonomyAbstract
We discuss the design and demonstration of highly efficient 1.55 µm hybrid III-V/Silicon semiconductor optical amplifiers (SOA). The optimized III-V wafer stack consists of Al0.10In0.71Ga0.18As multiple quantum wells (MQW) and Al0.48In0.52As electron stop layers to realize SOAs with high wall-plug efficiency (WPE). We present various designs and experimentally determine WPE values for 2 mW and 0.1 mW input power amplification. The 400 µm long flared SOA achieved the highest WPE value of 12.1% for output power > 10mW and the 400 µm long straight SOA achieved the highest WPE value of 7.3% for output power < 10mW. These are the highest WPE values ever obtained for 1.55 µm SOAs.
© 2015 Optical Society of America
1. Introduction
There has been extensive research in realizing large-scale integration of silicon (Si) photonics for long-haul communications, high-throughput optical interconnects, and future high performance computing (HPC) [1–6]. The impetus for this research lies in the fact that the silicon-on-insulator (SOI) platform is fully compatible with CMOS technology which drives mature IC technology and allows for a convergence with large-scale integrated photonics. Recent advances in key components such as high-contrast, low-loss arrayed waveguide gratings/routers (AWG/AWGR) [6, 7], athermal silicon ring modulators [8], germanium photo-detectors [9], hybrid SOAs [10–12], and single-wavelength hybrid laser sources [13, 14] have all paved a path towards realizing large chip-scale optical systems with various functionalities. Recently, the energy efficiency of these photonic components in an optical link have drawn strong attention with some projections indicating by 2020, the energy consumption of most components in 100-gigabit-per-second (Gbps) systems will be between a few pico-Joules (pJ) and sub-pJ per bit [2, 4, 5]. Therefore, over the past few years, there has been keen interest in heterogeneous integration of III-V compounds with silicon to realize monolithic integration of efficient hybrid devices [14]. The majority of hybrid III-V/Si technology is based on two prominent wafer-bonding techniques to address the challenge of realizing light emitters on silicon: (1) divinylsiloxane-benzocyclobutene (DVS-BCB) [15, 16], and (2) plasma-activated molecular bonding [12, 13, 17, 18]. However, other integration methods include flip-chip bonding commercially available lasers onto a silicon chip [19–21] and a more long term vision of III-V epitaxial growth on silicon substrates [22, 23]. This work utilizes the molecular bonding technique. The light source is an important component and is desirable in an energy and cost efficient dense-wavelength-division-multiplexing (DWDM) system. Also important are SOAs which can be used as amplifiers to compensate for optical losses from individual passive photonic elements such as ring resonators, MMIs, and AWG/AWGRs, etc. SOAs serve an important role in not only laser post-amplification, but in other diverse signal processing functionalities such as self-phase modulation (SPM), cross-gain modulation (XGM), and cross-phase modulation (XPM), etc [24, 25]. There have been several reports of III-V/Si hybrid SOAs [10, 11, 26, 27], however, none detailing optimized design strategies and experimental results demonstrating high WPE values for the III-V/Si platform. The authors from Ghent University have reported a hybrid SOA based on BCB bonding, however, WPE values could not be determined because device resistance values were not reported [10]. Work from the University of California at Santa Barbara (UCSB) showed that a WPE = 5.26% is possible, however, the tapers to convert the mode from the III-V mesa to silicon waveguide are not included [11, 26, 27]. In this paper, we demonstrate hybrid SOAs with III-V/Si tapers capable of achieving a WPE = 12.1% for 2 mW input power. We also present results for 0.1 mW input power amplification.
Table 1 shows a non-exhaustive list of the current commercial state-of-the-art and research SOAs (λ = 1550 nm) with their respective WPE values, where . Pin and Pout are SOA input and output powers respectively. The SOA drive current is Ibias and the voltage drop is Vbias. Section 2 will discuss parameters used for simulating the WPE optimization of hybrid SOAs using the same approach as [35]. The majority of this work discusses device fabrication and measurements respectively in section 3 and 4 respectively.
Table 1. Brief survey of state-of-the-art SOAs (λ = 1550nm) and WPE values
2. Device design and structure
There are mainly two material systems used for the fabrication of long-wavelength semiconductor amplifiers and lasers. However, for 1.55 µm operation, AlGaInAs/InP laser diodes have shown better performance than conventional InGaAsP/InP lasers, thus enabling continuous-wave (CW) operation at higher ambient temperatures. This is mainly attributed to the larger conduction band offset (ΔEc/ΔEg = 0.72 compared to ΔEc/ΔEg = 0.4) which reduces the amount of electron leakage from the MQW active region [36, 37]. The MQW active region for this design consists of eight 7 nm thick Al0.102In0.715Ga0.183As quantum wells with 1.28% compressive strain and seven 10 nm thick Al0.113In0.443Ga0.444As quantum barriers with −0.6% tensile strain. The MQW active region is sandwiched between two 80 nm thick Al0.182In0.528Ga0.290As i-SCH layers that also act as barriers. The photoluminescence (PL) peak is calculated to be 1530 nm and results in a gain peak at 1540 nm at room temperature operation. An Al0.480In0.520As electron stop layer is also included between the MQW and p-clad regions to prevent electron overflow. The bonding region consists of a 300 nm thick n-type InP layer (Si: 3E + 18 /cm3). The remaining p-type mesa is formed with p-InP and concluded with a 100 nm thick p-In0.53Ga0.47As contact layer (Zn: >1.0E + 19 /cm3). Table 2 shows the entire wafer stack description. The gain calculation for the QW is based on a 4x4-k•p band structure model which includes valence band mixing effects [38]. A Lorentz-broadening function with a scattering time of τsc = 0.03 ps scattering time is incorporated with the gain calculation. Figure 1(a) shows the corresponding optical gain for two temperatures of T = 25 °C and T = 90 °C. At room temperature, the transparent carrier density is Ntr = 1.46 x 1018 cm−3 and the initial differential gain is dg/dN = 1.88 x 10−15 cm2.
Table 2. 7 MQW III-V epitaxial wafer stack (nid: non-intentionally doped)
Fig. 1 (a) Calculated material gain for a single Al0.102In0.715Ga0.183As QW at T = 25 °C and T = 90 °C and (b) Calculated material gain spectrum for a single Al0.102In0.715Ga0.183As QW at T = 25 °C and T = 90 °C.
The optical mode in the hybrid SOA structure is shared by both the silicon waveguide and MQW region via evanescent coupling [27]. Consequently, the hybrid structure has one important design parameter, namely the multiple quantum well (MQW) confinement factor (ΓMQW) which is responsible for how much gain/absorption is within the optical mode. The ΓMQW can be adjusted by changing the silicon waveguide width for a given constant waveguide height. In general, for a fixed III-V wafer stack design, silicon height, and etch depth, the ΓMQW changes as the waveguide width is varied as shown in Fig. 2(b). This allows the output saturation power of an amplifier to be increased by decreasing ΓMQW [34]. The cross-section of the device is shown in Fig. 2(a) along with etched channels in the silicon layer that act as vertical out-gassing channels (VOC) [39]. Figures 2(c) and 2(d) illustrates the 2-D optical mode profiles in the high and low MQW confinement regions respectively. Outside the gain region, the silicon waveguides are tapered to a 3 µm width ending at the input/output facets of the device. The amplifier region itself can be broken down into two main parts consisting of the amplifier length and the III-V adiabatic taper length as shown in Fig. 2(a). For the purposes of integration and minimal gain ripple, it is important to take into consideration the III-V taper design so that any back reflections at the III-V/Si interface is suppressed. A 3D-finite-difference time-domain (FDTD) simulation concluded that a 100 µm long taper from a width of 4µm to 200nm with a 41° tilt angle at the tip will result in a reflection of 1.7E-5%. The output silicon waveguides are also angled at 7° to minimize the silicon/air interface reflection down to < 0.3%, as calculated by 3D-FDTD.
Fig. 2 (a) Cross section and top view of hybrid SOA with III-V taper regions, (b) MQW confinement factor vs. silicon waveguide width, (c) 2-D mode profile indicating high confinement region ΓMQW = 5.1%, and (d) low confinement region.
The PICS3DTM (Photonic Integrated Circuit Simulator in 3D) simulation program is employed to calculate the WPE of the straight section SOA. The model self-consistently solves 2-D carrier transport, optical gain calculation, and wave-guiding behavior within the transverse (x,y) and propagation planes (z). The SOA is characterized by the traveling wave rate eq. model in Eq. (1) where R, vg, Γ, g, αFC, N, α0, T are the signal amplitude, group velocity, confinement factor, QW material gain, free carrier absorption, carrier density, waveguide loss, and temperature respectively [40].
The evolution of the signal phase due to the band-to-band refractive index change and plasma effect is described in Eq. (2) and Δnplasma. The carrier density eq. is described by Eq. (3), where ηi, I, V, A, B, C are the internal quantum efficiency, injected current, active region volume, linear recombination, bi-molecular recombination, and Auger recombination coefficient respectively.By simulating SOA efficiency for various SOA widths and lengths, we can map out a design space for optimal WPE. It should be mentioned that the following simulations are performed for hydrophobic bonding, however, the designs should extend to hydrophilic bonding which is used throughout this paper [35]. As a brief explanation, the hydrophobic wafer-bonding approach is different from traditional hydrophilic wafer-bonding in that it yields no oxide interface between the III-V/Si interface, thus allowing maximum current carrier overlap with the optical mode. For the straight section hybrid SOA, we are mainly concerned with two design goals: 1) Pin = 2 mW, 10 dB internal gain, and 2) Pin = 0.1 mW, 10 dB internal gain. Figure 3(a) shows the WPE design space for the straight hybrid structure given the requirements of Pin = 20 mW, and 10 dB gain. For a straight hybrid structure, a theoretically estimated efficiency of 25% can be achieved for an assumed contact resistance of 2.4 × 10−4 Ω/cm2 at a junction temperature of 90 °C. Figure 3(b) shows the WPE design space for the straight hybrid structure given the requirements of Pin = 0.1 mW, and 10 dB gain.Fig. 3 Efficiency map of WPE for straight section hybrid SOA with (a) Pin = 2 mW and 10 dB gain with 3 Al0.250In0.679Ga0.071As MQW (T = 90°C), and (b) Pin = 0.1 mW and 10 dB gain.
Simulations were performed for different number of quantum wells for the case of Pin = 2 mW and it was determined the three quantum well (QW) design gave the highest WPE values. The peak WPE values are WPE = 23.25% for 2 QWs, WPE = 25.58% for 3 QWs, WPE = 25.47% for 6 QWs, WPE = 24.15% for 8 QWs. 3 QW design was chosen because of the highest WPE estimated from simulations, however, 8 QW design was also considered because of its reduced sensitivities to Auger recombination.
3. Device fabrication
Fabrication begins with a 6” SOI wafer which consists of a 500 nm thick top silicon layer and a 3 μm buried oxide (BOX) as shown in Fig. 4. The wafer goes through initial RCA-1 and RCA-2 cleaning and is then coated with 400 nm of Rohm Haas UV210-0.6 photoresist, soft-based at 130° C for 60 seconds and then exposed with a ASML PAS 5500 300 deep-UV lithography stepper using a 248nm-KrF light source at 18mJ/cm2 with appropriate focus correction. The sample goes through a 130° C post-exposure bake for 60 seconds and then developed in Rohm Haas MF26A developer for 60 seconds at 20° C In order to reduce the photoresist roughness due to the standing wave interference from the DUV exposure, we employ photoresist reflow at 156° C for 120 seconds. The silicon rib waveguide is patterned and etched 250 nm using an optimized hydrogen bromide (HBr) recipe [7]. This is then followed by a 500 nm etch to define the VOC and then the wafer is thoroughly cleaned using the RCA-1 and RCA-2 procedure to remove any organic/ionic contaminants and thin oxide layers. Surface treatment is then performed using oxygen plasma activation. The 3” III-V wafer is brought into physical contact with the 6” SOI wafer and then annealed at 300° C with an applied pressure of 1.0 MPa for two hours. Substrate removal of the III-V wafer is performed using HCl:H2O (3:1) which leaves a ~2 um thick III-V membrane consisting of the p-i-n stack described in Table 2. The 75 μm wide mesas are defined using lithography and Cr/AuZn (40/1000 Å) serves as a metal hard mask for subsequent mesa formation. The p-InGaAs contact and p-InP mesa layer are wet etched with H3PO4:H2O2:H2O (1:1:38) and HCl:H3PO4 (1:4) leaving a clean surface on top of the MQW region. The MQW is then wet etched using H3PO4:H2O2:H20 (1:1:38). After this, the n-contact is formed by evaporating a Ni/Ge/Au/Ni/Au (50/140/280/200/5000 Å) metal stack. Next, ion implantation lithography is performed for preventing lateral current spreading. This forces the carriers to funnel into a narrow channel for increased carrier overlap with the optical mode. A two step hydrogen (H + ) implantation at a 7° tilt and dosage of 5E + 13 /cm2 (1st profile: 120 keV, 2nd profile: 160 keV) is used for current narrowing. Next, the remaining n-InP outside the mesa region is removed with RIE etching using CH4:H2:Ar (40:10:20 sccm) at 25 mTorr with 100W RF power. The selectivity of this etch for InP to Si is better than 127 to 1.
Fig. 4 Fabrication flow for (a) 500nm tall silicon waveguide and VOC layers, (b) Cr/AuZn metal hard mask and III-V mesa definition, (c) N-contact metal lift-off, (d) additional p-contact metal, (e) H + proton implantation at 120keV and 160keV, (f) removing 300nm n-InP layer from passive sections, (g) 1µm SiO2 isolation layer, (h) thick Ti/Au metal probing pads.
A 1 μm thick PECVD SiO2 cladding/isolation layer is deposited and vias are etched for an additional evaporation of 1 μm thick Ti/Au probe metal pads. Rapid thermal annealing is finally performed at 340 °C for 30 seconds. Figures 5(a)-5(c) show the completed device. The devices are then diced and the facets are subsequently polished to a mirror finish. Initial electrical test characterization is performed with the 4-point probe method and the series resistance of an SOA of length 400 µm through the p-i-n junction is ~6.876 Ω. The n-contact and p-contact resistance are measured by performing a series of I-V measurements on 5 electrical pads known as the transmission line method (TLM). The n-contact resistance is measured to be ~8.81E-7 Ω-cm2.
Fig. 5 (a) Nomarski image of fabricated hybrid SOA, (b) Up-close image of III-V taper, and (c) cross-sectional SEM image.
4. Device characterization and discussion
Initial optical transmission measurements were carried out to determine the waveguide optical propagation and fiber coupling losses. The passive section without the III-V gain is used for measuring losses by coupling in and out of the waveguides with anti-reflection (AR) coated polarization maintaining (PM) tapered lensed fibers and into an optical vector network analyzer (OVNA). The OVNA utilizes interferometry to measure the intensity and phase information of the device and offers high spectral resolution (~50 MHz), and high dynamic range (90 dB) due to balanced detection. Polarization control is used to excite the TE light into the silicon waveguide which consists of 3 µm wide straight waveguides on the input/output facets and various waveguide widths in the gain region. The waveguide losses for widths of 500 nm, 600 nm, and 700 nm were determined to be respectively 1.128 dB/cm, 0.977 dB/cm, and 0.898 dB/cm. The loss values are calculated using the Fabry-Perot method defined as:, where L (2.5mm) is the cavity length, R1 and R2 are the facet power reflection, Pmax and Pmin are respectively the fringe power levels at the maximum and minimum. The power reflectivity at the facet is estimated at 42.2% from 3D-FDTD simulations. Furthermore, we carefully measured the coupling loss of the actual hybrid SOA devices by operating the SOA structure as a photo-detector by reverse biasing the active region and examining the extracted photocurrent for TE polarization for a given range of input power levels (Pin = 0 dBm to 19 dBm). Since the quantum efficiency of the SOA working as a photodetector is 0.9 – 1.0, the optical coupling loss at the facet can be estimated from the ratio of the number of generated photo-carriers and the given amount of incident photons calculated from the measured photocurrent and the input optical power. The estimated optical coupling loss was determined to be 13.74 dB, which is relatively high due to the thickness of the silicon layer (500 nm) chosen to achieve better active to passive waveguide transition for higher SOA WPE. We are currently addressing improvement of coupling efficiency by designing spot-size converter (SSC) fibers through collaboration with Chiral Optics, Inc. to achieve better mode matching between the fiber and the hybrid SOA waveguide interfaces. After facet polishing, the hybrid SOAs are mounted onto a temperature controlled stage kept at 20 °C. Continuous wave (CW) current injection through DC probe tips is used to forward bias the gain region. The polarization maintaining (PM) lensed fibers are anti-reflection (AR) coated and are angled at 23° to the normal of the input/output waveguide facet for maximum transmission, followed into a light-wave switch box (Agilent 86060C) which interconnects to a power meter (Agilent 8153A) and an OSA (Agilent 86142B). The 14 dB coupling loss at the input facet is compensated by using an Erbium Doped Fiber Amplifier (EDFA) with + 15 dB gain followed by an attenuator and a second EDFA with + 22 dB gain. For Pin = 2 mW, Fig. 6(a) shows the measured SOA chip transmission vs. CW drive current for the optimal amplifier length of 400 µm. The different lines plot output power vs. drive current for various silicon waveguide widths underneath the III-V active region, thus illustrating the role the MQW confinement factor has on SOA performance. As Fig. 6 indicates, the highest WPE = 9.2% has been achieved at 35 mA with the output power level of 7.0 dBm. Subsequently, for an output power of 10.1 dBm, we are able to achieve a WPE = 7.2% for an amplifier length of 400 µm and silicon width of 500 nm with a drive current of 95 mA as shown in Figs. 6(a)-6(b). Details of the I-V curves are shown in Fig. 6(a) with a forward resistance of approximately 3.46 Ω and a leakage current of 0.9 µA. SOA lengths of 500 µm, 600 µm, and 700 µm were measured, but a length of 400 µm performed the best. The main factor responsible for the gain saturation versus length is the amplified spontaneous emission (ASE), which causes a carrier density depletion in the SOA, thus we believe this is why the longer SOAs performed worse than the short ones. Essentially, when the SOAs are long enough, the end parts become transparent and do not contribute signal gain. It would have been interesting to see how shorter length hybrid SOAs (L< 400 µm) would have performed. Fabrication of shorter SOA lengths is underway and will be investigated in the near future. Figures 7(a) and 7(b) show the measured spectrum without including the output coupling loss. Gain ripple of contrast below 1 dB is observed (OSA resolution bandwidth = 0.06 nm) indicating that the reflections from the III-V taper region and 7° angled silicon waveguide/air interface have been sufficiently suppressed. Figure 8(a) shows the performance of the same SOA for Pin = 0.1 mW.
Fig. 6 (a) Amplifier power vs. current with Pin = 2 mW at T = 20 °C and I-V curve indicating 3.679 Ω series resistance, (b) Wall-plug-efficiency plot of ~7.2% for Pout = 10.11 dBm (SOA length = 400 µm, width = 4µm) WPE (%) = 100x(Pout-Pin)/(IbiasVbias).
Fig. 7 (a) Measured optical spectrum data for Pin = 2 mW without taking into account 14 dB output coupling loss (SOA length = 400 µm, width = 500nm) (b) close-up of signal gain spectrum (0.06 nm OSA resolution bandwidth).
Fig. 8 (a) Amplifier power vs. current with Pin = 0.1 mW at T = 20 °C, (b) Wall-plug-efficiency plot of ~0.38% for Pout = −2.43 dBm (SOA length = 400 µm, width = 500nm) WPE (%) = 100 × (Pout-Pin)/(IbiasVbias).
The flared output SOA has been a common way to increase the WPE by increasing the flared output saturation power through Eq. (4), where G0, w, d, a, τ, are the small signal gain, active region width, active region thickness, differential gain, and carrier lifetime respectively [34].
The saturation output power is increased by increasing the active region cross section wd and reducing the optical confinement factor Γ [41-45].We fabricated several flared SOA devices ranging from lengths of 400, 500, and 600µm, each with a tapered width from 4µm to 8µm, 6µm to 10µm, 8µm to 12µm, and 10µm to 14µm. The 400µm length worked the best and Figs. 9(a) and 9(b) show the measured amplifier power vs. drive current and the corresponding efficiency curves. For an input of 2 mW, we are able to extract 11.24 dBm output power, yielding a WPE = 12.1%. One thing we notice is that there was some improvement in the way the devices were mounted on our copper chuck. It should be noted that the gain for a flared SOA should be reduced compared to a straight section SOA for the same length due to reduced confinement factor and increased width. One possible explanation is that the III-V tapers for the straight SOA section had higher losses than for the flared SOA.Fig. 9 (a) Amplifier power vs. current with Pin = 2mW at T = 20 °C and I-V curve for different flared SOAs, (b) Wall-plug-efficiency plot of ~12.1% for Pout = 11.42dBm (SOA length = 400 µm, width = 4µm to 8µm) WPE (%) = 100 × (Pout-Pin)/(IbiasVbias).
Figures 10 and 11 show the measured amplifier power and WPE for an input power of −10 dBm. The coupling loss of the devices is verified by two methods: 1) insertion loss measurements of identical passive waveguide without the gain region, and 2) operating the SOA as a photo-detector with identical passive waveguide. Insertion loss measurements of a few identical passive waveguides with 7° angled output waveguides (input/output width = 3 µm) were performed and determined to be −27.65 dB. The passive waveguide can be mainly decomposed into 600 nm and 3000 nm wide waveguides with respective losses of 0.977 dB/cm and 0.401 dB/cm. These values are determined by separately conducted Fabry-Perot loss measurements on straight facets. Based on these values, the passive waveguide underneath the SOA has a waveguide loss of 0.158 dB and results in a coupling loss of 13.74 dB/facet. The coupling loss can also be determined by reverse biasing the SOA and using it as a photo-detector. The coupling loss is determined by -10log10[(# of electrons)/(# of photons)], where (# of electrons)/(# of photons) = (Iphotocurrent/q)/(Poptical/E) and where Poptical is the input power, Iphotocurrent is the generated photocurrent and E is the photon energy at 1550 nm. We can calculate the responsivity based on R = ηq/hf, where η is quantum efficiency, q is electric charge, h is plank's constant, and f is frequency. A responsivity of 1.185 A/W results in a quantum efficiency η = 0.95. Assuming a quantum efficiency of 0.95, the back calculated coupling loss is 13.73 dB/facet which matches well to our passive waveguide coupling loss measurement of 13.74 dB/facet.
Fig. 10 (a) Measured optical spectrum data for Pin = 2 mW without taking into account 14 dB output coupling loss (SOA length = 400 µm, width = 4µm to 8µm) (b) close-up of signal gain spectrum (0.06 nm OSA resolution bandwidth).
Fig. 11 (a) Amplifier power vs. current with Pin = 0.1mW at T = 20 °C and I-V curve for different flared SOAs, (b) Wall-plug-efficiency plot of ~0.4% for Pout = −2.5 dBm (SOA length = 400 µm, width = 4µm to 8µm) WPE (%) = 100 × (Pout-Pin)/(IbiasVbias).
Further improvement of the SOA chip gain and WPE may be achieved by optimizing the thermal management of the III-V/Si hybrid structure. Increased thermal extraction in the MQW region can be reduced by utilizing a 1 μm thick BOX. However, to achieve an efficient hybrid SOA, there is a need to consider optimal BOX thickness that balances both maximum thermal conductivity with minimum substrate leakage loss. We first consider a device length and width to be 500 μm and 4 μm respectively. If we assume a current injection of 100 mA and voltage drop of 1.5V it is possible to calculate the active region junction temperature T. Fig. 12(a) shows the III-V mesa temperature of the active MQW region vs. the III-V mesa width for various BOX thickness. The bottom of the 672µm thick Si substrate is held at 25 °C. For a constant III-V mesa width of 75 µm, changing the BOX thickness from 3 µm to 1 µm will reduce junction temperature by ~10 °C. As a design summary, the BOX thickness and III-V mesa width should be respectively 1 μm and 75 μm which allows for an operating device temperature of T = 51 °C and a substrate leakage loss below 0.1 dB/cm. Future hybrid active device temperatures can be significantly reduced by choosing the appropriate BOX thickness for increased operating efficiency.
Fig. 12 (a) III-V mesa temperature trade-off between BOX thickness, III-V mesa width and silicon substrate leakage loss. (b) Thermal simulation of the device with a 3 µm thick BOX layer, and (c) with a 1 µm thick BOX layer. Device length = 400 µm, width = 4 µm. Ibias = 100mA, Vbias = 1.5 V [35].
5. Conclusion
This paper examined the design and demonstration of straight section III-V/Si hybrid SOAs and their WPE performance at an operating wavelength of 1.55µm. We gave detailed design and simulation results which included 2-D carrier transport, MQW gain saturation effect, and optical wave-guiding in the transverse and propagation plane for the hybrid structure. Experimental results showed that high WPE was obtained for a SOA length of 400 µm. However, a systematic investigation on the reliability and optical losses of the III-V tapers should be evaluated to determine effects on WPE. For the 400 µm long device, the highest WPE value of 9.2% has been achieved, which is to date the highest WPE value for hybrid SOAs at 1550 nm and output power less than 10 mW. We also examine the performance of flared hybrid SOAs and find that we are able to achieve a WPE value of 12.1% for output powers larger than 10 mW. We have also presented a thermal analysis of the hybrid SOA with respect to BOX thickness so that maximum thermal conductivity can be achieved while keeping the silicon substrate optical leakage loss to a minimum. It was shown that a BOX thickness of 1 μm and a III-V mesa width of 75 μm was the optimum design in extracting heat while maintaining minimal substrate leakage loss.
References and links
1. M. J. R. Heck, J. F. Bauters, M. L. Davenport, J. K. Doylend, S. Jain, G. Kurczveil, S. Srinivasan, Yongbo Tang, and J. E. Bowers, “Hybrid silicon hotonic integrated circuit technology,” IEEE J. Sel. Top. Quantum Electron. 19(4), 6100117 (2013). [CrossRef]
2. M. J. R. Heck and J. E. Bowers, “Energy efficient and energy proportional optical interconnects for multi-core processors: driving the need for on-chip sources,” IEEE J. Sel. Top. Quantum Electron. 20(4), 332–343 (2014). [CrossRef]
3. M. J. R. Heck, H.-W. Chen, A. W. Fang, B. R. Koch, D. Liang, H. Park, M. N. Sysak, and J. E. Bowers, “Hybrid silicon photonics for optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 17(2), 333–346 (2011). [CrossRef]
4. R. S. Tucker, “Green optical communications-part I: energy limitations in transport,” IEEE J. Sel. Top. Quantum Electron. 17(2), 245–260 (2011). [CrossRef]
5. R. S. Tucker, “Green optical communications-part II: energy limitations in networks,” IEEE J. Sel. Top. Quantum Electron. 17(2), 261–274 (2011). [CrossRef]
6. R. Yu, S. Cheung, Y. Li, K. Okamoto, R. Proietti, Y. Yin, and S. J. B. Yoo, “A scalable silicon photonic chip-scale optical switch for high performance computing systems,” Opt. Express 21(26), 32655–32667 (2013). [CrossRef] [PubMed]
7. S. T. S. Cheung, B. Guan, S. S. Djordjevic, K. Okamoto, and S. J. B. Yoo, “Low-loss and high contrast silicon-on-insulator (SOI) arrayed waveguide grating,” in 2012 Conference on Lasers and Electro-Optics (CLEO) (OSA, 2012), pape CM4A.5. [CrossRef]
8. S. S. Djordjevic, K. Shang, B. Guan, S. T. S. Cheung, L. Liao, J. Basak, H.-F. Liu, and S. J. B. Yoo, “CMOS-compatible, athermal silicon ring modulators clad with titanium dioxide,” Opt. Express 21(12), 13958–13968 (2013). [CrossRef] [PubMed]
9. A. Novack, M. Gould, Y. Yang, Z. Xuan, M. Streshinsky, Y. Liu, G. Capellini, A. E.-J. Lim, G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “Germanium photodetector with 60 GHz bandwidth using inductive gain peaking,” Opt. Express 21(23), 28387–28393 (2013). [CrossRef] [PubMed]
10. S. Keyvaninia, G. Roelkens, D. Van Thourhout, J. M. Fedeli, S. Messaoudene, G. H. Duan, M. Lamponi, F. Lelarge, E. J. Geluk, and B. Smalbrugge, “A highly efficient electrically pumped optical amplifier integrated on a SOI waveguide circuit,” in 2012 IEEE 9th International Conference on Group IV Photonics (GFP) (IEEE, 2012), pp. 222–224. [CrossRef]
11. H. Park, A. W. Fang, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “A hybrid AlGaInAs-silicon evanescent amplifier,” IEEE Photonics Technol. Lett. 19(4), 230–232 (2007). [CrossRef]
12. P. Kaspar, R. Brenot, A. Le Liepvre, A. Accard, D. Make, G. Levaufre, N. Girard, F. Lelarge, G. H. Duan, N. Pavarelli, M. Rensing, C. Eason, G. Talli, P. O’Brien, S. Olivier, S. Malhouitre, C. Kopp, C. Jany, and S. Menezo, “Packaged hybrid III-V/silicon SOA,” in 2014 The European Conference on Optical Communication (ECOC) (IEEE, 2014), pp. 1–3. [CrossRef]
13. D. Guang-Hua, C. Jany, A. Le Liepvre, A. Accard, M. Lamponi, D. Make, P. Kaspar, G. Levaufre, N. Girard, F. Lelarge, J. M. Fedeli, A. Descos, B. Ben Bakir, S. Messaoudene, D. Bordel, S. Menezo, G. de Valicourt, S. Keyvaninia, G. Roelkens, D. Van Thourhout, D. J. Thomson, F. Y. Gardes, and G. T. Reed, “Hybrid III-V on silicon lasers for photonic integrated circuits on silicon,” IEEE J. Sel. Top. Quantum Electron. 20, 6100213 (2014).
14. C. Zhang, S. Srinivasan, Y. Tang, M. J. R. Heck, M. L. Davenport, and J. E. Bowers, “Low threshold and high speed short cavity distributed feedback hybrid silicon lasers,” Opt. Express 22(9), 10202–10209 (2014). [CrossRef] [PubMed]
15. S. Stankovic, R. Jones, M. N. Sysak, J. M. Heck, G. Roelkens, and D. Van Thourhout, “1310-nm hybrid III-V/si fabry-perot laser based on adhesive bonding,” IEEE Photonics Technol. Lett. 23(23), 1781–1783 (2011). [CrossRef]
16. S. Stankovic, R. Jones, M. N. Sysak, J. M. Heck, G. Roelkens, and D. Van Thourhout, “Hybrid III-V/si distributed-feedback laser based on adhesive bonding,” IEEE Photonics Technol. Lett. 24(23), 2155–2158 (2012). [CrossRef]
17. A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “Electrically pumped hybrid AlGaInAs-silicon evanescent laser,” Opt. Express 14(20), 9203–9210 (2006). [CrossRef] [PubMed]
18. A. W. Fang, H. Park, R. Jones, O. Cohen, M. J. Paniccia, and J. E. Bowers, “A continuous-wave hybrid AlGaInAs-silicon evanescent laser,” IEEE Photonics Technol. Lett. 18(10), 1143–1145 (2006). [CrossRef]
19. J. H. Lee, I. Shubin, J. Yao, J. Bickford, Y. Luo, S. Lin, S. S. Djordjevic, H. D. Thacker, J. E. Cunningham, K. Raj, X. Zheng, and A. V. Krishnamoorthy, “High power and widely tunable Si hybrid external-cavity laser for power efficient Si photonics WDM links,” Opt. Express 22(7), 7678–7685 (2014). [CrossRef] [PubMed]
20. S. Tanaka, S.-H. Jeong, S. Sekiguchi, T. Kurahashi, Y. Tanaka, and K. Morito, “High-output-power, single-wavelength silicon hybrid laser using precise flip-chip bonding technology,” Opt. Express 20(27), 28057–28069 (2012). [CrossRef] [PubMed]
21. A. J. Zilkie, B. J. Bijlani, P. Seddighian, D. C. Lee, W. Qian, J. Fong, R. Shafiiha, D. Feng, B. J. Luff, X. Zheng, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “High-efficiency hybrid III-V/si external cavity DBR laser for 3-μm SOI waveguides,” in Group IV Photonics Conference (IEEE, 2012), pp. 317–319. [CrossRef]
22. W. Metaferia, H. Kataria, S. Yan-Ting, and S. Lourdudoss, “Growth of InP directly on Si by corrugated epitaxial lateral overgrowth,” J. Phys. D Appl. Phys. 48(4), 045102 (2015). [CrossRef]
23. Z. Wang, C. Junesand, W. Metaferia, C. Hu, L. Wosinski, and S. Lourdudoss, “III-Vs on Si for photonic applications-a monolithic approach,” Mater. Sci. Eng., B 177(17), 1551–1557 (2012). [CrossRef]
24. T. Durhuus, B. Mikkelsen, C. Joergensen, S. L. Danielsen, and K. E. Stubkjaer, “All-optical wavelength conversion by semiconductor optical amplifiers,” J. Lightwave Technol. 14(6), 942–954 (1996). [CrossRef]
25. H. J. Lee, H. G. Kim, J. Y. Choi, and H. K. Lee, “All-optical clock recovery from NRZ data with simple NRZ-to-PRZ converter based on self-phase modulation of semiconductor optical amplifier,” Electron. Lett. 35(12), 989–990 (1999). [CrossRef]
26. Y.-h. Kuo, H. Park, A. W. Fang, J. E. Bowers, R. Jones, M. Paniccia, and O. Cohen, “High speed data amplification using hybrid silicon evanescent amplifier,” in 2007 Conference on Lasers & Electro-Optics/Quantum Electronics and Laser Science Conference (OSA, 2007), paper CTuII1. [CrossRef]
27. H. Park, A. W. Fang, and J. E. Bowers, “An electrically pumped hybrid silicon evanescent amplifier,” in 2007 Optical Fiber Communication Conference and Exposition National Fiber Optic Engineers Conference (OFCNFOEC) (OSA, 2007), paper OTuD2. [CrossRef]
28. Alphion, “Alphion SAO11b and SAC11b QLight booster amplifiers: SAO11b and SAC11b product brief,” https://www.components76.com/pdf_dir/369346_pr_file_1.pdf.
29. Alphion, “Alphion SAX20r, SAO20r, and SAC20r QLight swept source amplifiers: SAX20r, SAO20r, and SAC20r product brief,” http://www.sun-ins.com/lineup2/alphion/pdf-soa/SweptSource_8.5x11_draft3p_.pdf.
30. Covega, “Covega BOA 1007: C-band booster optical amplifier chip: Covega BOA 1007 Datasheet,” http://www.datasheetlib.com/datasheet/1146342/boa1007_covega-corporation.html.
31. Covega, “Covega BOA 1004: C-band booster optical amplifier: Covega BOA 1004 Datasheet,” http://www.datasheetlib.com/datasheet/1146309/boa1004_covega-corporation.html.
32. INPHENIX, “IPSAD1301/1304 & IPSAD1501/1504 (1310nm/1550nm): INPHENIX semiconductor optical amplifier device (gain-type) datasheet,” http://www.inphenix.com/pdfdoc/SOA_Device_Gain-type.pdf.
33. CIP-Photonics, “SOA L C-14 FCA: CIP SOALC14 Datasheet,” .
34. P. W. Juodawlkis, J. J. Plant, W. Loh, L. J. Missaggia, F. J. O’Donnell, D. C. Oakley, A. Napoleone, J. Klamkin, J. T. Gopinath, D. J. Ripin, S. Gee, P. J. Delfyett, and J. P. Donnelly, “High-power, low-noise 1.5-μm slab-coupled optical waveguide (SCOW) emitters: physics, devices, and applications,” IEEE J. Sel. Top. Quantum Electron. 17(6), 1698–1714 (2011). [CrossRef]
35. S. Cheung, Y. Kawakita, K. Shang, and S. J. B. Yoo, “Theory and design optimization of energy-efficient hydrophobic wafer-bonded III-V/si hybrid semiconductor optical amplifiers,” J. Lightwave Technol. 31(24), 4057–4066 (2013). [CrossRef]
36. J. Piprek, P. Abraham, and J. E. Bowers, “Self-consistent analysis of high-temperature effects on strained-layer multiquantum-well InGaAsP-InP lasers,” IEEE J. Quantum Electron. 36(3), 366–374 (2000). [CrossRef]
37. J. Piprek, J. K. White, and A. J. SpringThorpe, “What limits the maximum output power of long-wavelength AlGaInAs/InP laser diodes?” IEEE J. Quantum Electron. 38(9), 1253–1259 (2002). [CrossRef]
38. S. L. Chuang, “Efficient band-structure calculations of strained quantum wells,” Phys. Rev. B Condens. Matter 43(12), 9649–9661 (1991). [CrossRef] [PubMed]
39. D. Liang and J. E. Bowers, “Highly efficient vertical outgassing channels for low-temperature InP-to-silicon direct wafer bonding on the silicon-on-insulator substrate,” J. Vac. Sci. Technol., B 26, 1560–1568 (2008).
40. CrossLight, Crosslight Device Simulation Software Manual (Crosslight Software, 2011).
41. J. P. Donnelly, J. N. Walpole, G. E. Betts, S. H. Groves, J. D. Woodhouse, F. J. O’Donnell, L. J. Missaggia, R. J. Bailey, and A. Napoleone, “High-power 1.3-mu m InGaAsP-InP amplifiers with tapered gain regions,” IEEE Photonics Technol. Lett. 8(11), 1450–1452 (1996). [CrossRef]
42. J. P. Donnelly, J. N. Walpole, S. H. Groves, R. J. Bailey, L. J. Missaggia, and A. Napoleone, “High-power 1.5-μm InGaAsP/InP lasers with tapered-gain-region,” in 1997 IEEE Conference of Lasers and Electro-Optics Society (IEEE, 1996), pp. 405–406. [CrossRef]
43. F. Koyama, K. Y. Liou, A. G. Dentai, T. Tanbunek, and C. A. Burrus, “Multiple-quantum-well GaInAs/GaInAsP tapered broad-area amplifiers with monolithically integrated wave-guide lens for high-power applications,” IEEE Photonics Technol. Lett. 5(8), 916–919 (1993). [CrossRef]
44. J. N. Walpole, J. P. Donnelly, S. H. Groves, L. J. Missaggia, J. D. Woodhouse, R. J. Bailey, and A. Napoleone, “Diffraction-limited 1.3-μm-wavelength tapered-gain-region lasers with >1-W CW output power,” IEEE Photonics Technol. Lett. 8(11), 1429–1431 (1996). [CrossRef]
45. J. N. Walpole, E. S. Kintzer, S. R. Chinn, C. A. Wang, and L. J. Missaggia, “High-power strained-layer InGaAs/AlGaAs tapered traveling-wave amplifier,” Appl. Phys. Lett. 61(7), 740–741 (1992). [CrossRef]
