1. Introduction

Vertical-cavity surface-emitting semiconductor lasers (VCSELs), as special type of semiconductor lasers, have many advantages compared to edge-emitting semiconductor lasers, such as low cost in fabrication, low threshold current, compact size, circular output-beam profile and wafer-scale integration [1]. They have attracted some attentions to be applied in optical signal processing, optical buffer memories and optical interconnections. However, because of their circular transverse geometry, VCSELs can emit two linear-polarization (LP) lights (with the polarization direction along one of two orthogonal directions associated with crystalline or stress orientations, referred to x and y). And the polarization switching (PS) and the polarization bistability often occur when they are subjected to current or external light injection [2–10]. These phenomena are often considered as a drawback, degrading the laser performance. At present, they can also be generalized to apply some areas of great concern, such as polarization switch, polarization multiplexing and demultiplexing and optical logic gates devices [11–17]. It is a very attractive scheme that optical logic devices are designed by means of the PS of an optically injected VCSEL.

According to a few of recent studies, based on the PS in an optically injected VCSEL, there are several typical schemes for implementing different types of optoelectric logic gates and all-optical ones. For example, some logic gates, such as OR, NOR, and NAND, can be obtained by the interplay of the PS, the aperiodic current modulation and the spontaneous emission noise in an optically injected VCSEL [14]. Besides, the logical OR and AND can be implemented, using the interplay of the PS and the external light injection [15]. At last, the logical OR and AND can be performed, based on the interplay of the PS and the center frequency detuning between the master VCSEL and the slave one [16]. However, in these above-mentioned schemes, the PS is very sensitive to the injection current, optical injection strength and the center frequency detuning [6–10]. The slight perturbations of these parameters can induce the change of the polarization state. As a result, the output logic state will be varied. Therefore, these logic gates have poor stability. To achieve stability of these basic logic gates, the numerical values for the parameters of the laser need to be strictly limited in a small range [2–10]. In addition, only some basic logic gates can be implemented.

In our previous work [17], we proposed a novel scheme to control the PS in an optically injected VCSEL by electro-optic (EO) modulation, in which, with the increase of the applied electric field, the PS of the slave VCSEL with parallel optical injection (POI) appears periodic oscillation. The PS can be stably controlled when the applied electric field is fixed at a certain value. The results presented in our previous work will help to obtain different types of logic gates, which may be stably controlled by EO modulation. In this paper, we explore the implementation of some logic operations, such as AND, NAND, OR, NOR, XOR, XNOR and half-adder, using the PS of the optically injected VCSEL and the new EO modulation theory [18].

2. Theory and model

So far, the technology of the VCSEL with 850 nm tends to mature, its response frequency can be greater than 40GHz, and its transmission rate has reached 10Gb/s. On the other hand, the modulation frequency of EO modulator based LiNbO₃ crystal can reach 40GHz [19]. Therefore, the EO modulation speed of periodically poled LiNbO₃ (PPLN) can match the responce time of the VCSEL. Based on the above-mentioned consideration and the PS in an optically injected VCSEL, we present a scheme of optoelectric composite logic gate, shown in Fig. 1. Here, the M-VCSEL is master VCSEL; the S-VCSEL is slave VCSEL. The M-VCSEL and the S-VCSEL have both operating wavelength of 850nm and a threshold current of 6.8 mA. They are driven with a low noise current source (Tektronix LDC202 200mA), and temperature controlled within 0.01 °C. The optical isolator 1 (IS₁) ensures that the light from the output of M-VCSEL propagates unidirectionally to the polarization beam-splitter 1 (PBS₁). The IS₂ and the IS₃ are used to avoid the light from the PBS₂ to feed back into PPLN. The IS₄ ensures that the light from the PBS₃ is avoided to feed back into the S-VCSEL. An optical variable attenuator (VA) is placed in the left-side of the S-VCSEL to control optical injection strength. The applied electric filed E₀ is along the x-direction of the crystal coordinate system. Suppose that the light from the M-VCSEL propagates along the y-direction in the periodically poled LiNbO₃ (PPLN) crystal, the polar angle θ = π/2 and the azimuth angle φ = π/2. So for a uniaxial crystal PPLN, the unit vector of o-light and e-light a = (1, 0, 0) and b = (0,0,1). This means that the o-light and the e-light are along the x-direction and the z-direction in the PPLN crystal, respectively. With a fixed injection current, the M-VCSEL emits the x-LP and the y-LP components, which are separated by the PBS₁. The x-LP from the PBS₁ is considered as the original input of the o-light in the crystal because that the x-LP component is along the polarized direction of the o-light. The y-LP from the PBS₁ is considered as the original input of the e-light when it is aligned with the poarized direction of the e-light (z-direction) by the Faraday rotator 1 (FR₁) and the half wave plate1 (HWP₁). Under the effect of an applied electric field E₀, the two LP components are subject to EO amplitude modulation in the PPLN crystal. The output o-light from the PPLN, as the x-LP component, is parallel injected into the S-VCSEL by the mirror 2 and PBS2. The output e-light, as the y-LP component, is parallel injected into the S-VCSEL by the PBS2 when its polarized direction is aligned with the y-LP by the HWP₂ and the FR₂. The output x-LP and y-LP components from the S-VCSEL with POI are considered as the logic outputs Y₁ and Y₂, respectively.

 

Fig. 1 Schematic diagram of optoelectric composite logic gate based the VCSEL subjected to external optical injection, where M-VCSEL, master VCSEL; S-VCSEL, slave VCSEL; IS, isolator; PPLN, periodically poled LiNbO₃; μ_M and μ_S, the normalized injection current of the M-VCSEL and the S-VCSEL, respectively; PBS, polarization beam-splitter; POI, parallel optical injection; TEF, transverse electric field; HWP, half wave plate; FR, Faraday rotator; M, the mirror; VA, the variable attenutor. The applied electric field E₀ is digital square wave; A₁ and A₂, logic input signals; Y₁ and Y₂, logic output signals.

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Based on the spin flip model of VCSEL presented by Miguel [20], the rate equations of the M-VCSEL are modified as

From Fig. 1, it is known that the x-LP component is along the direction of the o-light from the PPLN crystal, and the y-LP component is aligned with the direction of the e-light by the FR₁ and HWP₁. Based on these conditions, the x-LP and y-LP components are considered as the original inputs of the o-light and e-light, respectively. So we have

When the two LP components subjected to EO modulation are injected into the S-VCSEL, we have

3. Results and discussions

First, we numerically calculate the Eqs. (1)-(3) and (21)-(23), using the four-order Rung-Kutta method. The numerical values in calculation are given in Table1, where n₁ and n₂ are from the Shellmeier refractive formula of the PPLN crystal [22]. The spontaneous emission noise terms in Eqs. (1) and (20) are ignored in the following calculation, owing to the slight influence on the PS of VCSEL [23]. According to the related reports [14–17], the PS or logic output states of an optically injected VCSEL depends on some key parameters, such as the injection current of the M-VCSEL and the S-VCSEL, μ_M and μ_S, as well as optical injection strength k_inj. As presented in [17], for any injection current μ_M of the M-VCSEL, with the increase of the applied electric field, the polarization of the S-VCSEL with POI oscillates periodically when μ_S = 1.2 and k_inj = 10ns⁻¹ (the same below). And the S-VCSEL may emit any polarization light if the applied electric field is fixed at a certain value. These results presented in [17] can help to realize various types of controllable optoelectric logic gates. On this basis, we suppose that the injection current μ_M equals to the sum of two square waves, μ_M = μ₁(t) + μ₂(t), that encode the two logic inputs. They are named as A₁ and A₂, respectively. Since the logic inputs can be either 0 or 1, there exist four distinct input sets: (0, 0), (0, 1), (1, 0), (1, 1). The logic input sets (0, 1) and (1, 0) yield the same μ_M value. Therefore, the four distinct logic sets is reduced to three μ_M values. Here, it should be more convenient that the parameters, such as the mean value μ₀, and the modulation amplitude Δμ, are introduced in this paper. So, instead of the four logic inputs, three injection current values, such as μ_M1 = μ₀-Δμ, μ_M2 = μ₀ and μ_M3 = μ₀ + Δμ, are considered as logic inputs. Besides, the x-LP and the y-LP from the S-VCSEL output are set as two logic outputs, Y₁ and Y₂. With only the x-LP component emitted from the S-VCSEL, Y₁ = 1 and Y₂ = 0; If the output of the S-VCSEL is only the y-LP component, Y₁ = 0 and Y₂ = 1. In this case, it is possible that some logic gates, such as AND, NAND, OR, NOR, XNOR, XOR and so on, are implemented. For this purpose, in the following we will elaborate the implementation scheme and logical operation method of the above-mentioned logic gates.

Table 1. Numerical values for optoelectric logic gates design

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Figure 2 shows the logic operations of some optoelectric composite logic gates, such as AND, NAND, OR, NOR, XNOR and XOR, when Δμ = 0.066, μ₀ = 1.114, μ_S = 1.2 and k_inj = 10ns⁻¹. Here, E₀ = 0kV/mm and E₀ = 1.326kV/mm are used to control logic gates; (A₁,A₂) = (0,0) when μ_M (μ₀-Δμ) = 1.048 [see Fig. 2(a)]; if μ_M = μ₀, (A₁,A₂) = (0,1) or (1,0); while μ_M (μ₀ + Δμ) = 1.18, (A₁,A₂) = (1,1). Besides, the logic symbol of the E₀ is defined as ${\tilde{E}}_0$.We suppose that ${\tilde{E}}_0$ = 0 when E₀ = 0kV/mm, and ${\tilde{E}}_0$ = 1 if E₀ = 1.326kV/mm. It is found from Fig. 2 that various digital signal processing, such as AND, NAND, OR, NOR, XNOR and XOR, are performed, using different logic operations of the applied electric field between the logic inputs A₁ and A₂. In the following, we take logical AND and NAND as an example to elaborate their logic operations.

 

Fig. 2 Time traces of the two logic inputs, the injection current, the applied electric field, the output x-LP and y-LP, and the logic outputs of AND, NAND, OR, NOR, XNOR and XOR operations when μ_S = 1.2 and k_inj = 10ns-1. Here, (a): time traces of the injection currents and its associated logic inputs; (b): AND and NAND operations; (c): OR and NOR operations; (d) XNOR and XOR operations.

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Firstly, we set ${\tilde{E}}_0$ = A₁·A₂ for logic AND and NAND operations [see Fig. 2(a) and (b)]. When (A₁, A₂) = (0, 0) and ${\tilde{E}}_0$ = 0, Y₁ = 0 and Y₂ = 1, owing to the case that the S-VCSEL outputs the y-LP component. If (A₁, A₂) = (1, 1) and ${\tilde{E}}_0$ = 1, Y₁ = 1 and Y₂ = 0 because that the output is the x-LP component. For (A₁, A₂) = (0, 1) or (1, 0) and ${\tilde{E}}_0$ = 0, Y₁ = 0 and Y₂ = 1 in the case of the output that is the y-LP component. So we obtain Y₁ = A₁·A₂, Y₂ = $\overline{A_1{A}_2}$. This means that the logic operations AND and NAND have been realized. As shown from Fig. 2(c) and (d), considering ${\tilde{E}}_0$ = A₁ + A₂, we obtain logic operations OR and NOR [see Fig. 2(c)]. Besides, logic operations XNOR and XOR are implemented when ${\tilde{E}}_0=\overline{A_1\oplus A_2}$[see Fig. 2(d)]. For above-mentioned logic gates, Tables 2–4 give the relationship between the logic inputs, the injection current, the applied electric field, the expected laser polarization and its associated logical outputs. From these tables, one sees that various logic operations, such as AND, NAND, OR, NOR, XNOR and XOR, can be performed by controlling the logical operations of the applied electric field between the two logic inputs.

Table 2. Relationship between the logic inputs, the injection current, the external applied electric field, the output polarization and the logic outputs for AND and NAND operations

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Table 3. Relationship between the logic inputs, the injection current, the external applied electric field, the output polarization and the logic output for OR and NOR operations

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Table 4. Relationship between the two logic inputs, the injection current, the external applied electric field, the output polarization and the logic output for XNOR and XOR operations

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To implement half-adder, we further present its schematic diagram, displayed in Fig. 3. Here, two slave VCSELs have the same injection current μ_s, and are subjected to the same optical injection. And μ_S = 1.2 and k_inj = 10ns⁻¹. In additional, two master VCSELs have the same injection current μ_M. The output x-LP component from the S-VCSEL1 is considered as the Carry (C) for half-adder; the output y-LP component from the S-VCSEL2 is assumed as the Sum (S) for half-adder; ${\tilde{E}}_{01}$ is the logic of the electric field applied on the PPLN1 crystal, ${\tilde{E}}_{02}$ denotes the logic of that applied on the PPLN2 crystal. Figure 4 displays the time traces of the logic inputs, the injection current μ_M, the applied electric field, the output polarization and the logic outputs of Carry and Sum for half-adder operation. Table 5 further shows the relationship between the logic inputs, the injection current, the external applied electric field, the output polarization and its associated logic output for the half-adder operation. From Fig. 4 and Table 5, it is found that, when ${\tilde{E}}_{01}$ = A₁⋅A₂, the Carry output is the AND operation (A₁⋅A₂) [see Fig. 4 (b)]. If ${\tilde{E}}_{02}=\overline{A_1\oplus A_2}$, the Sum is the XOR operation between A₁ and A₂. That is to say, S = A₁⊕A₂, C = A₁·A₂. This means that the logic operation of the half-adder can be implemented by controlling the logic operation of the applied electric field.

 

Fig. 3 Schematic diagram of the implementation scheme for logic half-adder operation Here, the upper system is used to realize Carry operation; the lower one is applied to implement Sum operation. The S-VCSEL1 and the S-VCSEL2 have the same injection current μ_s, and are subjected to the same optical injection. all parameters here are the same as that in Fig. 1; C represents the Carry output for half-adder, and S denotes the Sum output for half-adder; μ_M = μ₁ + μ₂.

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Fig. 4 The logic operation half-adder, time traces of the logic inputs, the injection currents, the applied electric field, the output polarization and the logic outputs of Carry and Sum for half-adder operation when μ_S = 1.2 and k_inj = 10ns⁻¹. Here, (a) the temporal waveforms of the injection current; (b) the output of Carry (C) and Sum (S) for half-adder. Here, E_S1x, and ${\tilde{E}}_{0\text{1}}$, the amplitude of the x-LP from the S-VCSEL1 and its associated logic, respectively; E_S2y and ${\tilde{E}}_{0\text{2}}$, the amplitude of the y-LP from the S-VCSEL2 and its associated logic, respectively.

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Table 5. Relationship between the logic inputs, the injection current, the external applied electric field, the output polarization and the logic output for the half-adder operation

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4. Conclusions

In the external optically injected system composed of master VCSEL and slave one, we put forward a novel implementation scheme for optoelectric logic operations, using the PS law of slave VCSEL and new EO modulation theory. In this scheme, the x-LP and y-LP components from the slave VCSEL output are considered as two logic outputs, which satisfy logic non operation. When the logic of the electric field applied on PPLN crystal is set as the AND, OR and XNOR operations between the two logic input signals, the output x-LP component, as one logic output, is the AND, OR and XNOR operations, respectively. The logic operations NAND, NOR and XOR are obtained from the other logic output (the output y-LP component). Based on the schemes of the logical AND and XOR, we further perform the half-adder operation. These results have potential applications in controllable optical logic gates with multifunction.